參數(shù)資料
型號: DM74LS74ASJX
廠商: Fairchild Semiconductor Corporation
英文描述: Dual D-Type Flip-Flop
中文描述: 雙D型觸發(fā)器
文件頁數(shù): 3/6頁
文件大小: 67K
代理商: DM74LS74ASJX
3
www.fairchildsemi.com
D
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 7:
All typicals are at V
CC
=
5V, T
A
=
25
°
C.
Note 8:
Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V
O
=
2.125V with the minimum
and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 9:
With all outputs OPEN, I
CC
is measured with CLOCK grounded after setting the Q and Q outputs HIGH in turn.
Switching Characteristics
at V
CC
=
5V and T
A
=
25
°
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 7)
V
I
V
OH
Input Clamp Voltage
HIGH Level
Output Voltage
V
CC
=
Min, I
I
=
18 mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max
V
IL
=
Max, V
IH
=
Min
I
OL
=
4 mA, V
CC
=
Min
V
CC
=
Max
V
I
=
7V
1.5
V
2.7
3.4
V
V
OL
LOW Level
Output Voltage
0.35
0.5
V
0.25
0.4
I
I
Input Current @ Max
Input Voltage
Data
Clock
Preset
0.1
0.1
0.2
mA
Clear
Data
Clock
0.2
20
20
I
IH
HIGH Level
Input Current
V
CC
=
Max
V
I
=
2.7V
μ
A
Clear
Preset
Data
40
40
0.4
0.4
0.8
0.8
100
8
I
IL
LOW Level
V
CC
=
Max
V
I
=
0.4V
Input Current
Clock
Preset
Clear
mA
I
OS
I
CC
Short Circuit Output Current
Supply Current
V
CC
=
Max (Note 8)
V
CC
=
Max (Note 9)
20
mA
mA
4
From (Input)
R
L
=
2 k
Symbol
Parameter
To (Output)
C
L
=
15 pF
Min
25
C
L
=
50 pF
Min
20
Units
Max
Max
f
MAX
t
PLH
Maximum Clock Frequency
MHz
Propagation Delay Time
LOW-to-HIGH Level Output
Clock to Q or Q
25
35
ns
t
PHL
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
Clock to Q or Q
30
35
ns
t
PLH
Preset to Q
25
35
ns
LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Preset to Q
30
35
ns
HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Clear to Q
25
35
ns
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
t
PHL
Clear to Q
30
35
ns
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