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參數(shù)資料
| 型號(hào)： | DM9000A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ethernet Controller with General Processor Interface |
| 中文描述： | 以太網(wǎng)控制器與通用處理器接口 |
| 文件頁數(shù)： | 13/56頁 |
| 文件大?。?/td> | 1744K |
| 代理商： | DM9000A |
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DM9000A
Ethernet Controller with General Processor Interface
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
13
6. Vendor Control and Status Register Set
The DM9000A implements several control and status
registers, which can be accessed by the host. These CSRs
are byte aligned. All CSRs are set to their default values by
hardware or software reset unless they are specified
Register
Description
Offset
Default value
after reset
00H
00H
00H
00H
00H
00H
00H
00H
37H
38H
00H
00H
40H
XXH
XXH
00H
Determined by
EEPROM
XXH
01H
XXH
00H
00H
00H
0CH
0A46H
9000H
18H
00H
00H
00H
00H
00H
00H
XXH
NCR
NSR
TCR
TSR I
TSR II
RCR
RSR
ROCR
BPTR
FCTR
FCR
EPCR
EPAR
EPDRL
EPDRH
WCR
PAR
Network Control Register
Network Status Register
TX Control Register
TX Status Register I
TX Status Register II
RX Control Register
RX Status Register
Receive Overflow Counter Register
Back Pressure Threshold Register
Flow Control Threshold Register
RX Flow Control Register
EEPROM & PHY Control Register
EEPROM & PHY Address Register
EEPROM & PHY Low Byte Data Register
EEPROM & PHY High Byte Data Register
Wake Up Control Register (in 8-bit mode)
Physical Address Register
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H-15H
MAR
GPCR
GPR
TRPAL
TRPAH
RWPAL
RWPAH
VID
PID
CHIPR
TCR2
OCR
SMCR
ETXCSR
TCSCR
RCSCSR
MRCMDX
Multicast Address Register
General Purpose Control Register (in 8-bit mode)
General Purpose Register
TX SRAM Read Pointer Address Low Byte
TX SRAM Read Pointer Address High Byte
RX SRAM Write Pointer Address Low Byte
RX SRAM Write Pointer Address High Byte
Vendor ID
Product ID
CHIP Revision
TX Control Register 2
Operation Control Register
Special Mode Control Register
Early Transmit Control/Status Register
Transmit Check Sum Control Register
Receive Check Sum Control Status Register
Memory Data Pre-Fetch Read Command Without Address
Increment Register
Memory Data Read Command With Address Increment
Register
Memory Data Read Command With Address Increment
Register
16H-1DH
1EH
1FH
22H
23H
24H
25H
28H-29H
2AH-2BH
2CH
2DH
2EH
2FH
30H
31H
32H
F0H
MRCMDX1
F1H
XXH
MRCMD
F2H
XXH
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