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參數(shù)資料
| 型號(hào)： | DM9000A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ethernet Controller with General Processor Interface |
| 中文描述： | 以太網(wǎng)控制器與通用處理器接口 |
| 文件頁數(shù)： | 14/56頁 |
| 文件大?。?/td> | 1744K |
| 代理商： | DM9000A |
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DM9000A
Ethernet Controller with General Processor Interface
Memory Data Read_ address Register Low Byte
Memory Data Read_ address Register High Byte
Memory Data Write Command Without Address Increment
Register
Memory Data Write Command With Address Increment
Register
Memory Data Write_ address Register Low Byte
Memory Data Write _ address Register High Byte
TX Packet Length Low Byte Register
TX Packet Length High Byte Register
Interrupt Status Register
Interrupt Mask Register
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
14
MRRL
MRRH
MWCMDX
F4H
F5H
F6H
00H
00H
XXH
MWCMD
F8H
XXH
MWRL
MWRH
TXPLL
TXPLH
ISR
IMR
FAH
FBH
FCH
FDH
FEH
FFH
00H
00H
XXH
XXH
00H
00H
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
P = power on reset default value
H = hardware reset default value
S = software reset default value
6.1 Network Control Register (00H)
Bit
Name
7
RESERVED
PH0,RW
E = default value from EEPROM
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read
and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
Default
Description
Reserved
Wakeup Event Enable work in 8-bit mode
When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
Reserved
PHS0,RW Force Collision Mode, used for testing
PHS0,RO
Full-Duplex Mode of the internal PHY.
Loopback Mode
Bit 2 1
0 0 Normal
0 1 MAC Internal loopback
1 0 Internal PHY 100M mode digital loopback
1 1 (Reserved)
PH0,RW
Software reset and auto clear after 10us
6
WAKEEN
P0,RW
5
4
3
RESERVED
FCOL
FDX
0,RO
2:1
LBK
PHS00,
RW
0
RST
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| DM9000A_06 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
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