參數(shù)資料
型號(hào)： DM9000E
廠商： Electronic Theatre Controls, Inc.
英文描述： ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY
中文描述： ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片
文件頁(yè)數(shù)： 7/54頁(yè)
文件大?。?/td> 575K
代理商： DM9000E
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9000-DS-F02
June 26, 2002
7
5. Pin Description
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,
LI= reset Latch Input, #= asserted low
5.1 MII Interface
Pin No.
Pin Name
I/O
Description
37
LINK_I
I
External MII device link status
41,40,39,
38
43
RXD [3:0]
I
External MII Receive Data
4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode
External MII Carrier Sense
Active high to indicate the pressure of carrier, due to receive or transmit activities
in 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface.
External MII Collision Detect. This pin is output in reverse MII interface.
CRS
I/O
44
COL
I/O
45
RX_DV
I
External MII Receive Data Valid
46
RX_ER
I
External MII Receive Error
47
RX_CLK
I
External MII Receive Clock
49
TX_CLK
I/O
External MII Transmit Clock. This pin is output in reverse MII interface.
53,52,51,
50
TXD [3:0]
O
External MII Transmit Data
4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps
nibble mode
TXD [2:0] is also used as the strap pins of IO base address.
IO base = (strap pin value of TXD [2:0]) * 10H + 300H
External MII Transmit Enable
54
TX_ EN
O
56
MDIO
I/O
MII Serial Management Data
57
MDC
O
MII Serial Management Data Clock
This pin is also used as the strap pin of the polarity of the INT pin
When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin
is high active
Note: The pins of MII interface are all have a pulled down resistor about 60k ohm internally
5.2 Processor Interface
1
IOR#
I
Processor Read Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Processor Write Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Address Enable
A low active signal used to select the DM9000.
2
IOW#
I
3
AEN
I
4
IOWAIT
O
Processor Command Ready
When a command is issued before last command is completed, the IOWAIT will
be pulled low to indicate the current command is waited
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9000E-H 功能描述:以太網(wǎng)開(kāi)發(fā)工具 ETHERNET CONTROLLER HEADER BRD 50x40mm RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
DM9000EP 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 100LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 100LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 100LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Digital IC Case Style:LQFP; No. of Pins:100; Interface Type:MII; Operating Temperature Min:0C;;RoHS Compliant: Yes
DM9000電路圖-1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:型號(hào)DM9000電路圖1
DM9000電路圖-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DM9000電路圖-2
DM9002CJ/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad 2-input NAND Gate
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