參數(shù)資料
型號: DM9601
廠商: Electronic Theatre Controls, Inc.
英文描述: USB Ethernet MAC Controller with Intergrated 10/100 PHY
中文描述: USB以太網(wǎng)MAC控制器與集成10/100網(wǎng)卡芯片
文件頁數(shù): 24/58頁
文件大?。?/td> 603K
代理商: DM9601
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
24
Final
Version: DM9601-DS-F01
June 22, 2002
10.15 Wake Up Control Register ( 0FH )
Bit
7:6
5
Name
Type
0,RO
0,RW
Description
RESERVED
LINKEN
Reserved
When set, enable Link Status Change Wake-up Event.
This bit will not be affected after a software reset.
When set, enable Sample Frame Wake-up Event.
This bit will not be affected after a software reset.
When set, enable Magic Packet Wake-up Event.
This bit will not be affected after a software reset.
When set, indicates link change and Link Status Change Event occurred.
This bit will not be affected after a software reset.
When set, indicates the sample frame is received and Sample Frame Event
occurred. This bit will not be affected after a software reset.
When set, indicates the Magic Packet is received and Magic packet Event
occurred. This bit will not be affected after a software reset.
4
SAMPLEEN
0,RW
3
MAGICEN
0,RW
2
LINKST
0,RO
1
SAMPLEST
0,RO
0
MAGICST
0,RO
10.16 Physical Address Register ( 10H~15H )
Bit
7:0
7:0
7:0
7:0
7:0
7:0
Name
PAB5
PAB4
PAB3
PAB2
PAB1
PAB0
Default
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
Description
Physical Address Byte 5 (15H)
Physical Address Byte 4 (14H)
Physical Address Byte 3 (13H)
Physical Address Byte 2 (12H)
Physical Address Byte 1 (11H)
Physical Address Byte 0 (10H)
10.17 Multicast Address Register ( 16H~1DH )
Bit
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Name
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
Default
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
X,RW
Description
Multicast Address Byte 7 (1DH)
Multicast Address Byte 6 (1CH)
Multicast Address Byte 5 (1BH)
Multicast Address Byte 4 (1AH)
Multicast Address Byte 3 (19H)
Multicast Address Byte 2 (18H)
Multicast Address Byte 1 (17H)
Multicast Address Byte 0 (16H)
10.18 General purpose control Register ( 1EH )
Bit
7
6:0
Name
RESERVED
GEP_CNTL
Default
0,RO
1,RW
Description
Reserved
General purpose control:
Define the input/output direction of General Purpose Register
When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. GPIO0 default is output for POWER_DOWN function. Others default are
input
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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