參數(shù)資料
型號: DMA2275
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
元件分類: 消費家電
英文描述: DMA 2275, DMA 2286 C/D/D2-MAC Descrambler
中文描述: SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 16/48頁
文件大小: 217K
代理商: DMA2275
DMA 2275, DMA 2286
16
Table 8–3:
IM Bus register of the DMA 2286
Address
Label
Bit No.
Function
203
C1A
C1E
C1U
C1M
0–9
10
11
12–15
channel 1 packet address
channel 1 packet selection enable
channel 1 mode update
channel 1 mode
linear/nicam
hamming/parity protection
high/medium quality
stereo/mono
194
see register 203
channel 2
195
see register 203
channel 3
196
see register 203
channel 4
197
SFS
CD
AUM
DRS
0–10
13
14
15
subframe select
SFS = sample number of the first bit in the selected subframe
examples:
DRS = 1,
first subframe
DRS = 1,
second subframe SFS = 106
DRS = 0,
first subframe
chip definition
0 = DMA 2271/2281
1 = DMA 2286
auto mode
0 = auto mode off
1 = sound coding in packet header
data rate select
0 = 10.125 Mb/s
1 = 20.25 Mb/s
SFS = 7
SFS = 14
undelayed packet output of sound proc.
packet output delayed by 128
μ
s
D2 MAC
C/D MAC
198
CS
14, 15
chip select
0 = imbus of DMA 2271/2281 active
1 = imbus of DMA 2286 active
204
SBE
DGT
P0R
P0C
DSB
0–3
4–7
8
9
10
s_bus enable, each bit enables one s_bus channel
channel 1 enable
channel 2 enable
channel 3 enable
channel 4 enable
data group type selection
packet 0 reset
1: select first byte in packet 0 buffer (first byte = data group type DGT)
packet 0 clear
1: enable packet 0 buffer to store next packet 0
disable s_bus data output (pin 66)
0 = enabled
1 = high impedance
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