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參數(shù)資料
| 型號(hào)： | DP5Z2MW16PH3-15C |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 5V PROM MODULE, 120 ns, QFP48 |
| 封裝： | HERMETIC SEALED, CERAMIC, GULLWING, MODULE, SLCC-48 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 4549K |
| 代理商： | DP5Z2MW16PH3-15C |
Dense-Pac Microsystems, Inc.
DP5Z2MW16Pn3
PRELIMINARY
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard
microprocessor bus cycles.
Table 1: Bus Operation
Mode
CE
OE
WE
A0
A1
A9
I/O0-I/O15
Read 1
VIL
VIH
X
DOUT
Output Disable 1
VIL
VIH
X
HIGH-Z
Standby 1
VIH
X
HIGH-Z
Deep Power-Down 1
X
HIGH-Z
Manufacturer Identifier 1, 3
VIL
VIH
VIL
VID
00C2H
Device Identifier 3
VIL
VIH
VIL
VID
00F1H
Write 1, 2
VIL
VIH
VIL
X
DIN
NOTES:
1. X can be VIL or VIH for address or control pins.
2. Command for deferent Erase operations, Data program operations or Selector Protect operations can only be successfully completed through proper
command sequence.
3. VID = 11.5V - 12.5V.
WRITE OPERATION
Commands are written to the COMMAND INTERFACE REGISTER
(CIR) using standard microprocessor write timing. The CIR serves
as the interface between the microprocessor and the internal chip
operation. The CIR can decipher Read Array, Read Silicon ID,
Erase and Program command. In the event of a read command,
the CIR simply points the read path at either the array or the Silicon
ID, depending on the specific read command given. for a program
or erase cycle, the CIR informs the write state machine that a
program or erase has been requested. During a program cycle,
the write state machine control the program sequences and the
CIR will only respond to status reads. During a sector/chip erase
cycle, the CIR will respond to status reads and erase suspend. After
the writhe state machine has completed its task, it will allow the
CIR to respond to its full command set. The CIR stays at read status
register mode until the microprocessor issues another valid
command sequence.
Device operations are selected by writing commands into the CIR.
Table 3 below defines 16 Megabit Flash family command.
PIN NAMES
A0 - A19
ADDRESS INPUTS: for memory address. Addresses are internally latched during a write cycle.
I/O0 - I/O15
DATA INPUT/OUTPUT: Input data and command during Command Data Interface Register (CIR) write
cycles. Outputs array, status and identifier data in the appropriate read mode. Floated when the chip is
de-selected or the outputs are disabled.
CE
CHIP ENABLE INPUT: Activate the device’s control logic, Input buffers, decoders and sense amplifiers. With
CE high, the device is de-selected and power consumption reduces to Standby level upon completion of any
current program or erase operation. CE must be low to select the device. Device selection occurs with the
falling edge of CE. The rising edge of CE disables the device.
WE
WRITE ENABLE: Controls writes to the Command Interface Register (CIR). WE is active low.
OE
OUTPUT ENABLE: Gates the device’s data through the output buffers during a read cycle. OE is active low.
VDD
DEVICE POWER SUPPLY (+5.0 Volts
±10%)
VSS
GROUND
N.C.
No Connect
30A161-22
REV. B
3
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