參數(shù)資料
型號(hào)： DP5Z2MW16PH3-15C
元件分類： PROM
英文描述： 2M X 16 FLASH 5V PROM MODULE, 120 ns, QFP48
封裝： HERMETIC SEALED, CERAMIC, GULLWING, MODULE, SLCC-48
文件頁(yè)數(shù)： 16/21頁(yè)
文件大小： 4549K
代理商： DP5Z2MW16PH3-15C
DP5Z2MW16Pn3
Dense-Pac Microsystems, Inc.
PRELIMINARY
DEVICE OPERATION
SILICON ID READ
The Silicon ID Read mode allows the reading out of a binary code
from the device and will identify its manufacturer and type. this is
intended for use by programming equipment for the purpose of
automatically matching the device to be programmed with its
corresponding programming algorithm. This mode is functional
over the entire temperature range of the device.
To activate the mode, the programming equipment must force VID
(11.5V ~ 12.5V) on address pin A9. Two identifier bytes may then
be sequenced from the device outputs by toggling address A0 from
VIL to VIH. All addresses are don’t cares except A0 and A1.
The manufacturer and device codes may also be read via the
command register, for instance when the device is erased or
programmed in a system without access to high voltage on the A9
pin. The command sequence is illustrated in Table 2.
To terminate the operation, it is necessary to write the read/reset
command sequence into the CIR.
READ RESET COMMAND
The read or reset operation is initiated by writing the read/reset
command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The device
remains enabled fro reads until the CIR contents are altered by a
valid command sequence.
The device will automatically power-up in the read/reset state. In
this case, a command sequence is not required to read data. This
default value ensures that no spurious alteration of the memory
content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Table 2: Command Definition
Command
Sequence
Bus
Cycles
Req’d
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Address Data Address Data Address Data
Address
Data
Address Data Address Data
Read/Reset
4
5555H AAH 2AAAH 55H 5555H F0H
RA
RD
-
Silicon ID Read
4
5555H AAH 2AAAH 55H 5555H 90H 00H/01H C2H/F1H
-
Page/Byte Program
4
5555H AAH 2AAAH 55H 5555H A0H
PA
PD
-
Chip Erase
6
5555H AAH 2AAAH 55H 5555H 80H
5555H
AAH
2AAAH 55H 5555H 10H
Sector Erase
6
5555H AAH 2AAAH 55H 5555H 80H
5555H
AAH
2AAAH 55H
SA
30H
Erase Suspend
3
5555H AAH 2AAAH 55H 5555H B0H
-
Erase Resume
3
5555H AAH 2AAAH 55H 5555H D0H
-
Read Status Register
4
5555H AAH 2AAAH 55H 5555H 70H
X
SRD
-
Clear Status Register
3
5555H AAH 2AAAH 55H 5555H 50H
-
Sleep
3
5555H AAH 2AAAH 55H 5555H C0H
-
Abort
3
5555H AAH 2AAAH 55H 5555H E0H
-
NOTES:
Address bit A15 - A19 = X = Don’t Care for all address commands except for Programming Address (PA) and Sector Address (SA).
5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.
Bus operations are defined in Table 2.
RA = Address of the memory location to be read.
PA = Address of the memory to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A16 - A19 will be uniquely select any sector.
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
SRD = Data read from Status Register.
Table 3: Silicon ID Code
Type
A19
A18
A17
A16
A1
A0
Code
(HEX)
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Manufacturer’s
Code
X
VIL
00C2H
1
0
1
0
Device Code
X
VIL
VIH
00FIH
1
0
1
30A161-22
REV. B
4
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