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參數(shù)資料
| 型號： | DP84412J |
| 英文描述： | DRAM Controller |
| 中文描述： | DRAM控制器 |
| 文件頁數(shù)： | 42/46頁 |
| 文件大?。?/td> | 644K |
| 代理商： | DP84412J |
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13.0 Errata for DP8440/41
ERRATUM
Y
1
While programmed in Normal Mode, the RAS signals may
negate
(/2
clock before the CAS signals for the last burst
access. This can be a problem for write accesses, in which
the RAS hold time may not be met for some DRAM arrays.
Recommended Fix
The RAS assertion time can be extended
(/2
clock by hold-
ing off the negation of the BSTARQ signal (Burst Access
Request) until after the falling edge of the last DTACK. If
this approach is taken, then BSTARQ must then be negated
before the clock edge which negates the last DTACK to
guarantee no other accesses take place.
TL/F/11718–36
ERRATUM
Y
2
The NoWrap signal and EXTNDRF signal are multiplexed
on the same pin. NoWrap is asserted when doing sequential
burst acceses that don’t wrap around. EXTNDRF (Extend
Refresh) is used to extend a refresh while it is occurring.
A problem arises when a NoWrap burst access occurs
slightly before or during a refresh cycle. The DP8440/41
goes into a refresh cycle, however, because the NoWrap/
EXTNDRF signal is asserted, the refresh cycle may last in-
definitely and the access will never complete.
Recommended Fix
The designer must be reminded that NoWrap/EXTNDRF
are multiplexed and if NoWrap acceses are used in the de-
sign, it is recommended that the NoWrap be gated with the
RFIP signal as outlined below.
TL/F/11718–37
ERRATUM
Y
3
The NoWrap signal and BSTARQ (Burst Request) signal
should not be asserted on the same clock edge. This is only
a problem when doing NoWrap burst accesses.
Recommended Fix
The NoWrap signal should be asserted from ONE clock af-
ter the BSTARQ signal is asserted. This will have no effect
on the operation of the burst access and will prevent any
problems from occurring.
ERRATUM
Y
4
When using external refreshes, the start of an access may
be delayed slightly if the access occurs near the assertion
of the RFRQ (Refresh Request) signal.
Recommended Fix
There is no guarantee the access will begin immediately
after the assertion of ADS, therefore, the internal timing sig-
nals, DTACK or NADTACK, should always be used as a
reference to generate the acknowledge signal to the CPU.
Delayed Access due to RFRQ
TL/F/11718–44
42
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DP84412N | DRAM Controller |
| DP8441VLJ | DRAM Controller |
| DP84422BN | DRAM Controller |
| DP84422J | DRAM Controller |
| DP84422N | DRAM Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DP84412J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84412N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84412N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84412N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP8441VLJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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