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參數(shù)資料
| 型號： | DP84422J |
| 英文描述： | DRAM Controller |
| 中文描述： | DRAM控制器 |
| 文件頁數(shù)： | 29/46頁 |
| 文件大小： | 644K |
| 代理商： | DP84422J |
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8.0 Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Temperature Under Bias
0
§
C to
a
70
§
C
b
65
§
C to
a
150
§
C
Storage Temperature
All Input and Output Voltage
with Respect to GND
b
0.5V to
a
7V
ESD Rating
2000V
Recommended Operating
Conditions
Supply Voltage, V
CC
Operating Free Air Temperature
4.75V to 5.25V
0
§
C to
a
70
§
C
9.0 DC Electrical Characteristics
T
A
e
0
§
C to
a
70
§
C, V
CC
e
5V
g
5%, GND
e
0V
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IH
Logical 1 Input Voltage
Tested with a Limited
Functional Pattern
2.00
V
CC
a
0.5
V
V
IL
Logical 0 Input Voltage
Tested with a Limited
Functional Pattern
b
0.5
0.8
V
V
OH1
Q and WE Outputs
I
OH
e b
10 mA
V
CC
b
1.0
V
V
OL1
Q and WE Outputs
I
OL
e
10 mA
0.5
V
V
OH2
All Outputs Except Qs, WE
I
OH
e b
5 mA
V
CC
b
1.0
V
V
OL2
All Outputs Except Qs, WE
I
OL
e
5 mA
0.5
V
I
IN
Input Leakage Current
V
IN
e
V
CC
or GND
b
10
10
m
A
I
CC2
Supply Current
CLK at 40 MHz (I/Os Active)
260
mA
C
IN
Input Capacitance
f
IN
at 1 MHz
5
10
pF
10.0 Load Capacitance
Q0–11
C
L
e
50 pF
WE
C
L
e
50 pF
RAS0–3
C
L
e
50 pF
CAS0–3
C
L
e
50 pF (DP8440)
CAS0–7
C
L
e
50 pF (DP8441)
Other outputs C
L
e
50 pF
Adder Table for Higher Capacitive Loads
Output
ns/10 pF
Linear up to
Maximum Load
Q0–11
0.350
360 pF max
WE
0.548
500 pF max
RAS0–3
0.282
125 pF max
CAS0–3
0.282
125 pF max (DP8440)
CAS0–7
0.334
67 pF max (DP8441)
11.0 AC Timing Parameters
Two speed selections are given, the DP8440/41-40 and the
DP8440/41-25. The differences between the two parts are
the maximum operating frequencies of the input CLKs and
the maximum delay specifications. Low frequency applica-
tions may use the ‘‘-40’’ part to gain improved timing.
The AC timing parameters are grouped into sectional num-
bers as shown below. These numbers also refer to the tim-
ing diagrams.
1–6
Clock Parameters
50–53
TRI-STATE Parameters
100–109
Refresh Parameters
200–203
Programming Parameters
300–325
Common Parameters
400–423
Fast access parameters used in burst and Page
Mode accesses
29
相關PDF資料 |
PDF描述 |
|---|---|
| DP84422N | DRAM Controller |
| DP84432J | DRAM Controller |
| DP84432N | DRAM Controller |
| DP8472 | Floppy Disk Controller |
| DP8472J | Floppy Disk Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DP84422J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84422N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84422N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84422N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| DP84432J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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