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參數(shù)資料

4.0 Programming and Resetting

4.1 RESET

After power up, the DP8440/41 must be reset and pro-

grammed before it can be used to access the DRAM. Reset

is accomplished by asserting the input RESET for at least

16 positive edges of CLK after V

stabilizes. After reset,

the part can be programmed.

4.2 PROGRAMMING

Programming is accomplished by presenting a valid pro-

gramming selection on the row, column, bank selects and

ECAS inputs and toggling the ML input from low to high.

When ML goes high the part is programmed. After the first

programming after a reset the part will enter a 60 ms initiali-

zation period. During this period the controller will refresh

the memory, so further DRAM warm up cycles are not nec-

essary. The user can program the part on the fly by pulsing

ML low and high (provided that no refresh is in progress)

while a valid programming selection is on the address bus.

The part will not enter the initialization period when it is only

re-programmed.

TL/F/11718–4

FIGURE 5. Reset

TL/F/11718–5

FIGURE 6. Programming

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
DP84432N/A+	制造商:未知廠家制造商全稱:未知廠家功能描述:DRAM Controller
DP84432N/B+	制造商:未知廠家制造商全稱:未知廠家功能描述:DRAM Controller
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DP8451J-3	制造商:未知廠家制造商全稱:未知廠家功能描述:Disk Data Separator/Synchronizer
DP8451J-4	制造商:未知廠家制造商全稱:未知廠家功能描述:Disk Data Separator/Synchronizer

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