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參數(shù)資料
| 型號： | DS1045S-5 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 16TAP 16-SOIC |
| 標準包裝： | 45 |
| 標片/步級數(shù)： | 16 |
| 功能： | 多重，可編程 |
| 延遲到第一抽頭： | 9ns |
| 接頭增量： | 5ns |
| 可用的總延遲： | 84ns |
| 獨立延遲數(shù)： | 2 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 管件 |
DS1045
2 of 6
PARALLEL PROGRAMMING
Parallel programming of the DS1045 is accomplished via the set of parallel inputs A0-A3 and B0-B3 as
shown in Figure 1. Parallel input A0-A3 and B0-B3 accept TTL levels and are used to set the delay
values of outputs OUTA and OUTB, respectively. Sixteen possible delay values between the minimum
9ns delay and the maximum delay of the DS1045-x device version can be selected using the parallel
programming inputs A0-A3 or B0-B3 (see Table 2, “Delay vs. Programmed Input”). For example, the
DS1045-3 outputs OUTA or OUTB and can be programmed to produce 16 possible delays between the
9ns (minimum) and the 54ns (maximum) in 3ns increment levels.
For applications that do not require frequent reprogramming, the parallel inputs can be set using fixed
logic levels, as would be produced by jumpers, DIP switches, or TTL levels as produced by computer
systems. Maximum flexibility in parallel programming can be achieved when inputs are set by computer-
generated data. By using the enable input pins for each respective programmed output and observing the
input setup (tDSE) and hold time (tDHE) requirements, data can be latched on an 8-bit bus. If the enable
pins, EA and EB , are not used to latch data, they should be set to a logic level 1. After each change in the
programmed delay value, a settling time (tEDV) or (tPDV) is required before the delayed output signal is
reliably produced. Since the DS1045 is a CMOS design, undefined input pins should be connected to well
defined logic levels and not left floating.
PART NUMBER TABLE Table 1
PART NUMBER
STEP ZERO DELAY
MAX DELAY TIME
MAX DELAY
TOLERANCE
DS1045-3
9
±=1ns
54ns
±2.5ns
DS1045-4
9
±=1ns
69ns
±3.3ns
DS1045-5
9
±=1ns
84ns
±4.1ns
NOTE:
Additional delay step times are available from Dallas Semiconductor by special order. Consult factory for
availability.
BLOCK DIAGRAM Figure 1
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