參數(shù)資料
型號(hào)： DS10BR254TSQ/NOPB
廠商： National Semiconductor
文件頁數(shù)： 13/16頁
文件大小： 0K
描述： IC LVDS REPEAT 1.5GBPS 1:4 40LLP
標(biāo)準(zhǔn)包裝： 1
類型： 轉(zhuǎn)發(fā)器
Tx/Rx類型： LVDS
延遲時(shí)間： 440ps
電容 - 輸入： 1.7pF
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 135mA
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-LLP-EP（6x6）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
其它名稱： DS10BR254TSQDKR
SNLS260D – DECEMBER 2007 – REVISED APRIL 2013
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
Differential Propagation Delay Low to
440
650
ps
High(1)
RL = 100
tPHLD
Differential Propagation Delay High to
400
650
ps
Low(1)
tSKD1
Pulse Skew |tPLHD tPHLD|
(1) (2)
40
100
ps
tSKD2
Channel to Channel Skew(1)(3)
40
125
ps
tSKD3
Part to Part Skew(1)(4)
50
200
ps
tLHT
Rise Time(1)
150
300
ps
RL = 100
tHLT
Fall Time(1)
150
300
ps
tON
Any PWDN to Output Active Time
8
20
μs
tOFF
Any PWDN to Output Inactive Time
5
12
ns
tSEL
Select Time
5
12
ns
JITTER PERFORMANCE(1)
tRJ1
VID = 350 mV
135 MHz
0.5
1
ps
VCM = 1.2V
tRJ2
311 MHz
0.5
1
ps
Random Jitter
Clock (RZ)
(RMS Value)(5)
tRJ3
503 MHz
0.5
1
ps
tRJ4
750 MHz
0.5
1
ps
tDJ1
VID = 350 mV
270 Mbps
6
22
ps
VCM = 1.2V
tDJ2
622 Mbps
6
21
ps
Deterministic Jitter
K28.5 (NRZ)
(Peak to Peak Value)(6)
tDJ3
1.0625 Gbps
9
18
ps
tDJ4
1.5 Gbps
9
17
ps
tTJ1
VID = 350 mV
270 Mbps
0.01
0.03
UIP-P
VCM = 1.2V
tTJ2
622 Mbps
0.01
0.03
UIP-P
PRBS-23 (NRZ)
Total Jitter(7)
tTJ3
1.0625 Gbps
0.01
0.04
UIP-P
tTJ4
1.5 Gbps
0.01
0.06
UIP-P
(1)
Specification is specified by characterization and is not tested in production.
(2)
tSKD1, |tPLHD tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(3)
tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(4)
tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(5)
Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(6)
Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(7)
Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
6
Copyright 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS10BR254
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