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參數(shù)資料
| 型號： | DS1267S-100+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DUAL DIGITAL 100K 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 750 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 3 線串口 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
DS1267
3 of 12
102199
DS1267 BLOCK DIAGRAM Figure 1
I/O SHIFT REGISTER Figure 2
Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value.
When wiper position data is to be written to the DS1267, 17 bits (or some integer multiple) of data should
always be transmitted. Transactions which do not send a complete 17-bits (or multiple) will leave the
register incomplete and possibly an error in the desired wiper positions.
After a communication transaction has been completed, the RST signal input should be taken to a low
state to prevent any inadvertent changes to the device shift register. Once RST has reached a low state,
the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position.
A new wiper position will only engage after a RST transition to the inactive state. On device power-up
the DS1267 wiper positions will be set at 50% of the total resistance or binary value 1000 0000.
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