參數(shù)資料
型號: DS12885QN+
廠商: Maxim Integrated Products
文件頁數(shù): 9/22頁
文件大小: 0K
描述: IC RTC W/RAM 128 BYTE IND 28PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 37
類型: 時鐘/日歷
特點: 警報器,夏令時,閏年,NVSRAM,方波輸出
存儲容量: 114B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.5 V ~ 4 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 管件
產(chǎn)品目錄頁面: 1435 (CN2011-ZH PDF)
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
____________________________________________________________________
17
Bit 7: Interrupt Request Flag (IRQF). This bit is set to
1 when any of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
Any time the IRQF bit is 1, the IRQ pin is driven low.
This bit can be cleared by reading Register C or with a
RESET.
Bit 6: Periodic Interrupt Flag (PF). This bit is read-
only and is set to 1 when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0
bits establish the periodic rate. PF is set to 1 indepen-
dent of the state of the PIE bit. When both PF and PIE
are 1s, the IRQ signal is active and sets the IRQF bit.
This bit can be cleared by reading Register C or with a
RESET.
Bit 5: Alarm Interrupt Flag (AF). A 1 in the AF bit indi-
cates that the current time has matched the alarm time.
If the AIE bit is also 1, the IRQ pin goes low and a 1
appears in the IRQF bit. This bit can be cleared by
reading Register C or with a RESET.
Bit 5: Update-Ended Interrupt Flag (UF). This bit is
set after each update cycle. When the UIE bit is set to
1, the 1 in UF causes the IRQF bit to be a 1, which
asserts the IRQ pin. This bit can be cleared by reading
Register C or with a RESET.
Bits 3 to 0: Unused. These bits are unused in Register
C. These bits always read 0 and cannot be written.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IRQF
PF
AF
UF
0
Control Register C
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VRT
0000000
Control Register D
Bit 7: Valid RAM and Time (VRT). This bit indicates
the condition of the battery connected to the VBAT pin.
This bit is not writeable and should always be 1 when
read. If a 0 is ever present, an exhausted internal lithi-
um energy source is indicated and both the contents of
the RTC data and RAM data are questionable. This bit
is unaffected by RESET.
Bits 6 to 0: Unused. The remaining bits of Register D
are not usable. They cannot be written and they always
read 0.
MSB
LSB
MSB
LSB
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