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參數(shù)資料
| 型號(hào)： | DS1330YP-70-IND |
| 英文描述： | 256k Nonvolatile SRAM with Battery Monitor |
| 中文描述： | 256k非易失SRAM與電池監(jiān)視器 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 191K |
| 代理商： | DS1330YP-70-IND |
DS1330Y/AB
7 of 11
POWER-DOWN/POWER-UP TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
V
CC
Fail Detect to
CE
and
WE
Inactive
t
PD
V
CC
slew from V
TP
to 0V
t
F
t
RPD
V
CC
slew from 0V to V
TP
t
R
t
PU
V
CC
Valid to End of Write Protection
t
REC
V
CC
Valid to
RST
Inactive
t
RPU
V
CC
Valid to
BW
Valid
t
BPU
MIN
TYP
MAX
1.5
UNITS
NOTES
11
s
150
s
s
V
CC
Fail Detect to
RST
Active
15
14
150
s
V
CC
Valid to
CE
and
WE
Inactive
2
ms
125
350
ms
ms
150
200
14
1
s
14
BATTERY WARNING TIMING
(t
A
: See Note 10)
PARAMETER
SYMBOL
Battery Test Cycle
t
BTC
Battery Test Pulse Width
t
BTPW
Battery Test to
BW
Active
t
BW
MIN
TYP
24
MAX
UNITS
hr
s
s
NOTES
1
1
(t
A
= 25 C)
PARAMETER
SYMBOL
Expected Data Retention Time
t
DR
MIN
10
TYP
MAX
UNITS
years
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high-impedance state.
3.
t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4.
t
DS
is measured from the earlier of
CE
or
WE
going high.
5.
These parameters are sampled with a 5pF load and are not 100% tested.
6.
If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition, the output
buffers remain in a high-impedance state during this period.
7.
If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in high-impedance state during this period.
8.
If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high-impedance state during this period.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1330BL-70-IND | NVRAM (Battery Based) |
| DS1330WP-150 | NVRAM (Battery Based) |
| DS1330YL-100 | NVRAM (Battery Based) |
| DS1330YL-100-IND | NVRAM (Battery Based) |
| DS1330YL-70 | NVRAM (Battery Based) |
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| DS1336N | 功能描述:IC AFTERBURNER IND 16-DIP RoHS:否 類別:集成電路 (IC) >> PMIC - O 圈控制器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 應(yīng)用:電池備份，工業(yè)/汽車，大電流開關(guān) FET 型:- 輸出數(shù):5 內(nèi)部開關(guān):是 延遲時(shí)間 - 開啟:100ns 延遲時(shí)間 - 關(guān)閉:- 電源電壓:3 V ~ 5.5 V 電流 - 電源:250µA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC N 包裝:帶卷 (TR) |
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