參數(shù)資料
型號: DS1339U-3
英文描述: TRANS NPN BIPOL DUAL 160V SOT363
中文描述: 串行實時時鐘
文件頁數(shù): 5/18頁
文件大小: 279K
代理商: DS1339U-3
DS1339 I
2
C Serial Real-Time Clock
5 of 18
POWER-UP/DOWN CHARACTERISTICS
(T
A
= -40C to +85°C) (Note 1, Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Recovery at Power-Up
t
REC
(Note 14)
2
ms
V
CC
Fall Time; V
PF(MAX)
to V
PF(MIN)
t
VCCF
300
s
V
CC
Rise Time; V
PF(MIN)
to V
PF(MAX)
t
VCCR
0
s
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in
battery-backup mode.
Note 1:
Limits at -40°C are guaranteed by design and are not production tested.
Note 2:
SCL only.
SDA and SQW/
INT
.
Note 3:
Note 4:
I
CCA
—SCL at f
SC
max, V
IL
= 0.0V, V
IH
= V
CC
, trickle charger disabled.
Specified with the I
2
C bus inactive, V
IL
= 0.0V, V
IH
= V
CC
, trickle charger disabled.
Using recommended crystal on X1 and X2.
Note 5:
Note 6:
Note 7:
After this period, the first clock pulse is generated.
Note 8:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IHMIN
of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
Note 9:
The maximum t
HD:DAT
need only be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 10:
A fast-mode device can be used in a standard-mode system, but the requirement t
SU:DAT
to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
R(MAX)
+
t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line
is released.
Note 11:
C
B
—total capacitance of one bus line in pF.
Guaranteed by design. Not production tested.
Note 12:
Note 13:
The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V
V
CC
V
CCMAX
and 1.3V V
BACKUP
3.7V.
This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay occurs.
Note 14:
Figure 1. Power-Up/Down Timing
OUTPUTS
V
CC
V
PF(MAX)
V
PF(MIN)
INPUTS
HIGH-Z
DON'T CARE
VALID
RECOGNIZED
RECOGNIZED
VALID
t
VCCF
t
VCCR
t
REC
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