參數(shù)資料
型號: DS1342U+
廠商: Maxim Integrated Products
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC RTC I2C W/ALARM 8USOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 50
類型: 時鐘/日歷
特點: 警報器,閏年,方波輸出
時間格式: HH:MM:SS(12/24 小時)
數(shù)據格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 1.8 V ~ 5.5 V
電壓 - 電源,電池: 1.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-uMAX
包裝: 管件
10
Maxim Integrated
Low-Current I2C RTCs for High-ESR Crystals
DS1341/DS1342
when the interface timeout is exceeded, prior to the
acknowledge, the incomplete byte of data is not written.
Clock and Calendar (00h–06h)
The time and calendar information is obtained by read-
ing the appropriate register bytes. The RTC registers are
illustrated in Table 1. The time and calendar are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The Day register
increments at midnight and rolls over from 7 to 1. Values
that correspond to the day-of-week are user-defined
but must be sequential (i.e., if 1 equals Sunday, then 2
equals Monday, and so on). The CENT bit in the Month
register toggles when the Years register rolls over from
99 to 00. Illogical time and date entries result in an unde-
fined operation.
The DS1341/DS1342 can be run in either 12hr or 24hr
mode. Bit 6 of the Hours register is defined as the 12hr
or 24hr mode select bit. When high, the 12hr mode is
selected. In the 12hr mode, bit 5 is the AM/PM bit, with
a content of 1 being PM. In the 24hr mode, bit 5 is the
second bit of the 10hr field. The century bit (bit 7 of the
Month register) is toggled when the Years register incre-
ments from 99 to 00. On a power-on reset (POR), the
time and date are set to 00:00:00 01/01/00 (hh:mm:ss
DD/MM/YY) and the Day register is set to 01.
Alarms (07h–0Dh)
The DS1341/DS1342 contain two time-of-day/date
alarms. Alarm 1 can be set by writing to registers 07h–
0Ah. Alarm 2 can be set by writing to registers 0Bh–0Dh.
The alarms can be programmed to activate the CLKIN/
INTA or SQW/INTB outputs (see Table 5) on an alarm
match condition. Bit 7 of each of the time of day/date
alarm registers are mask bits. When all the mask bits for
each alarm are 0, an alarm only occurs when the values
in the timekeeping registers 00h–06h match the values
stored in the time of day/date alarm registers. The alarms
can also be programmed to repeat every second, min-
ute, hour, day, or date. Tables 2 and 3 show the possible
alarm settings. Configurations not listed in the tables
result in illogical operation. POR values are undefined.
The DY/DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/DT is written to 0, the alarm is the result
of a match with date of the month. If DY/DT is written to
1, the alarm is the result of a match with day of the week.
Table 2. Alarm 1 Mask Bits
Table 3. Alarm 2 Mask Bits
X = Don’t care.
DY/DT
ALARM 1 MASK BITS (BIT 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
Alarm once per second.
X
1
0
Alarm when seconds match.
X
1
0
Alarm when minutes and seconds match.
X
1
0
Alarm when hours, minutes, and seconds match.
0
Alarm when date, hours, minutes, and seconds match.
1
0
Alarm when day, hours, minutes, and seconds match.
DY/DT
ALARM 2 MASK BITS (BIT 7)
ALARM RATE
A2M4
A2M3
A2M2
X
1
Alarm once per minute (00 second of every minute).
X
1
0
Alarm when minutes match.
X
1
0
Alarm when hours and minutes match.
0
Alarm when date, hours, and minutes match.
1
0
Alarm when day, hours, and minutes match.
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