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參數(shù)資料
型號: DS1554WP-120
廠商: Maxim Integrated Products
文件頁數(shù): 16/18頁
文件大?。?/td> 0K
描述: IC RTC RAM Y2K 3.3V 120NS 34-PCM
標(biāo)準(zhǔn)包裝: 40
類型: 時鐘/日歷
特點: 警報器,閏年,NVSRAM,監(jiān)視計時器,Y2K
存儲容量: 32KB
時間格式: HH:MM:SS(24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 2.97 V ~ 3.63 V
電壓 - 電源,電池: 3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 34-PowerCap? 模塊
供應(yīng)商設(shè)備封裝: 34-PowerCap 模塊
包裝: 托盤
DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM
7 of 18
Table 2. Register Map
DATA
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION/RANGE
7FFFh
10 Year
Year
00-99
7FFEh
X
10
Month
01-12
7FFDh
X
10 Date
Date
01-31
7FFCh
X
FT
X
Day
01-07
7FFBh
X
10 Hour
Hour
00-23
7FFAh
X
10 Minutes
Minutes
00-59
7FF9h
OSC
10 Seconds
Seconds
00-59
7FF8h
W
R
10 Century
Century
Control
00-39
7FF7h
WDS
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
Watchdog
7FF6h
AE
Y
ABE
Y
Interrupts
7FF5h
AM4
Y
10 Date
Date
Alarm Date
01-31
7FF4h
AM3
Y
10 Hours
Hours
Alarm Hours
00-23
7FF3h
AM2
10 Minutes
Minutes
Alarm Minutes
00-59
7FF2h
AM1
10 Seconds
Seconds
Alarm Seconds
00-59
7FF1h
Y
Unused
7FF0h
WF
AF
0
BLF
0
Flags
X = Unused, Read/Writeable under Write and Read Bit Control
AE = Alarm Flag Enable
Y = Unused, Read/Writeable without Write and Read Bit Control
ABE = Alarm in Battery-Backup Mode Enable
FT = Frequency Test Bit
AM1-AM4 = Alarm Mask Bits
OSC = Oscillator Start/Stop Bit
WF = Watchdog Flag
W = Write Bit
AF = Alarm Flag
R = Read Bit
0 = 0 (Read Only)
WDS = Watchdog Steering Bit
BLF = Battery Low Flag
BMB0 to BMB4 = Watchdog Multiplier Bits
RB0 to RB1 = Watchdog Resolution Bits
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The
OSC bit is the
MSB of the Seconds Register (B7 of 7FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1554 is shipped from Maxim with the clock oscillator turned off,
OSC bit set to a 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (7FF8h).
As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is
set to a 0 for a minimum of 500
s. The read bit must be a zero for a minimum of 500 s to ensure the
external registers will be updated.
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