參數(shù)資料
型號: DS1672S-2
廠商: Maxim Integrated Products
文件頁數(shù): 13/15頁
文件大小: 0K
描述: IC TIMEKEEPER 2V 32-BIT 8-SOIC
標準包裝: 100
類型: 二進制計數(shù)器
特點: 涓流充電器
時間格式: 二進制
數(shù)據(jù)格式: 二進制
接口: I²C,2 線串口
電源電壓: 1.8 V ~ 2.2 V
電壓 - 電源,電池: 1.3 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
DS1672
7 of 15
PIN DESCRIPTION
PIN
NAME
FUNCTION
1, 2
X1, X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator
circuitry is designed for operation with a crystal having a specified load
capacitance (CL) of 6pF. For more information about crystal selection and
crystal layout considerations, refer to Application Note 58: Crystal
Considerations with Dallas Real-Time Clocks. The DS1672 can also be driven
by an external 32.768kHz oscillator. In this configuration, the X1 pin is
connected to the external oscillator signal and the X2 pin is left unconnected.
3
VBACKUP
Battery Input for Any Standard 3V Lithium Cell or Other Energy Source.
Battery voltage must be held between 1.3V and 3.63V for proper operation.
Diodes placed in series between the power source and the VBACKUP pin may
result in improper operation. If a backup supply is not required, VBACKUP must
be grounded. UL recognized to ensure against reverse charging current when
used in conjunction with a lithium battery (charger disabled). See “Conditions
of Acceptability” at www.maxim-ic.com/qa/info/ul.
4
GND
Ground.
5
SDA
Serial-Data Input/Output. SDA is the input/output pin for the I
2C serial
interface. The SDA pin is open drain and requires an external pullup resistor.
6
SCL
I
2C Serial-Clock Input. SCL is used to synchronize data movement on the
serial interface and requires an external pullup resistor.
7
RST
Active-Low Reset Output. It functions as a microprocessor reset signal. This
pin is an open-drain output and requires an external pullup resistor.
8
VCC
Power pin for Primary Power Supply. When VCC is applied within normal
limits, the device is fully accessible and data can be written and read. When
VCC is below VPF, reads and writes are inhibited.
Figure 3. Recommended Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
GND
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