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參數(shù)資料
| 型號： | DS1844S-100/T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DIG QUAD 100K 20-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 接片： | 64 |
| 電阻（歐姆）： | 100k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 750 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | 2 線串行（設備位址）或 5 線串行 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
DS1844
3 of 14
When writing data, the R/ W input should be in a low state. Once RST has activated the port, a data bit is
latched (or valid) on the low-to-high transition of the CLK signal. Once, eight low-to-high transitions
have occurred on the CLK input, the associated 8-bit data block will be loaded as the wiper’s value on the
falling edge of the eighth clock pulse. Potentiometer wiper values can be loaded in any order. Also,
potentiometer wiper data can be loaded 1, 2, 3, or 4 bytes at a time. When RST transitions from high to
low, the 5-wire port will be disabled.
While RST is high and R/ W is low, (the write or load state) the cascade data output, DOUT will be
inhibited; preventing the passing of data from DIN to DOUT . However, when RST is low data is passed
directly from DIN to DOUT .
When reading data, the R/ W input should be in a high state. Once RST has enabled the port, data can be
clocked out of the device and will appear on the DOUT terminal. A data bit will be valid on the falling
edge of a clock pulse after a maximum time period of 20 ns (of that falling edge). Data will appear on
DOUT most significant bit (MSB) first and starting with potentiometer-0, followed by potentiometer-1 and
so forth.
2-Wire Addressable Serial Port Control
The 2-wire serial port interface supports a bi-directional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device which generates the serial clock
(SCL), controls the bus access, and generates the START and STOP conditions. The DS1844 operates as
a slave on the two-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The 2-wire serial port is selected when the port select input, PS, is in a high-state. The following I/O
terminals control the 2-wire serial port: SDA, SCL, A0, A1, A2, PS=1. Timing diagrams for the 2-wire
serial port can be found in Figures 4 through 8. Timing information for the 2-wire serial port is provided
in the AC Electrical Characteristics table for 2-wire serial communications.
The following bus protocol has been defined (See Figure 4).
-
Data transfer may be initiated only when the bus is not busy.
-
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes
in the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH
defines a START condition.
Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is
HIGH defines the STOP condition.
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