參數(shù)資料
型號: DS1852B-00C+
廠商: Maxim Integrated Products
文件頁數(shù): 16/26頁
文件大?。?/td> 0K
描述: IC MONITOR TXRX OPTICAL 25-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 103
類型: 收發(fā)器
電源電壓: 2.7 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 25-TFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 25-BGA(5x5)
包裝: 托盤
DS1852
23 of 26
NOTES
1) All voltages are referenced to ground.
2) This is the time for one comparison. The complete cycle is this value multiplied by 3.
3) Absolute voltage error for Bin, Pin, and Rin are valid from 0% to 98%.
4) ASEL = GND, SDA = SCL = Din = Fin = Lin = RSin = VCC.
5) The time to begin monitoring operations after VCC has risen above the analog minimum voltage.
6) After STOP command has been received. No acknowledges will be issued during this interval.
7) A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250ns must
then be met. This will automatically be the case if the device does not stretch the low period of the
SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next
data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
8) After this period, the first clock pulse is generated.
9) The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the
SCL signal.
10) A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH MIN of
the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
11) C
B— total capacitance of one bus line in picofarads, timing referenced to 0.9VCC and 0.1VCC.
12) Input levels equal either VCC or GND.
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