The ADC reads a total of five inputs: VCC (i" />
參數(shù)資料
型號(hào)： DS1852B-00C+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 23/26頁(yè)
文件大?。?/td> 0K
描述： IC MONITOR TXRX OPTICAL 25-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 103
類(lèi)型： 收發(fā)器
電源電壓： 2.7 V ~ 5.5 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 25-TFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 25-BGA（5x5）
包裝： 托盤(pán)
DS1852
6 of 26
ANALOG-TO-DIGITAL CONVERTER
The ADC reads a total of five inputs: VCC (internal), temperature (internal), and external inputs Bin, Pin,
and Rin. All conversions are updated every 13ms (nominal) or 20ms (max) in rotation. The conversions
are absolute and compared to an internal reference. While the 16-bit values are read, only the upper 12
are significant. The lower four bits are undefined.
The temperature and analog voltage inputs are calibrated by Dallas Semiconductor and read with the
following scale:
Temperature: High byte: -128
°C to +127°C signed; low byte: 1/256°C. The lower four bits
should be ignored.
S
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
VCC: This reads as an unsigned 16-bit quantity at 100
mV LSB, with a maximum range of
6.5535V, when using the factory default value. The lower four bits should be ignored.
Bin, Pin, Rin: These read as an unsigned 16-bit quantity at 38.147
mV LSB, with a maximum range
of 2.500V, when using factory default values. The lower four bits should be ignored.
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
Each analog input has a 16-bit scaling calibration in Table 03h EEPROM. This allows the analog
conversion values to be calibrated for full scale at any input voltage from 0.2V to 6.5535V. The ADC
conversion value will clamp rather than roll over. Each external analog channel has a maximum input
voltage of VCC independent of the calibration factor.
The upper four bits of scaling select the coarse range; the lower 12 bits are for fine adjustments. The
algorithm to trim the scale is described below.
The scaling factors for each input (VCC, VBin, VPin, and VRin) are 16 bits wide. They are located in
Table 03h at addresses C8h to CFh, respectively. The 16 bits are a combination of two trims. The lower
12 bits are binary weighted and give the high resolution trim for scaling the input to output relationship.
The upper four bits are a coarse-adjust of the lower 12 bits. In other words, the upper four bits scale the
LSB value of the binary weighted lower 12 bits.
As an illustration, assume a value of 1V is needed to read full scale. Force a voltage less than 1V
(975mV, for example) to keep clamping out of the way. The closer to max voltage the better, but not too
close.
1) Set the scale trim to 0FFFh (the upper four bits to all zeros and the lower 12 bits to all ones).
2) Use a SAR approach on the upper four bits, starting with 1000b, to find the smallest 4-bit trim
necessary to cause the voltage reading to be above the input (in this case, greater than or equal to
975mV). If they all clamp, that is okay. That means 0000b is the needed value for the upper four
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