參數(shù)資料
型號(hào): DS1854E-050
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 5/22頁(yè)
文件大?。?/td> 0K
描述: IC RES TEMP-CNTRL 50/50K 16TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 50 ppm/°C
存儲(chǔ)器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 95°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
DS1854
Dual Temperature-Controlled
Resistors with Two Monitors
____________________________________________________________________
13
MEMORY
LOCATION
EEPROM/
SRAM
R/W
DEFAULT
SETTING
NAME OF LOCATION
FUNCTION
1C to 5F
EEPROM
00
Reserved
60 to 61
SRAM
R
Measured TMP
(MSB to LSB)
Digitized measured value for temperature.
See Table 1.
62 to 63
SRAM
R
Measured VCC
(MSB to LSB)
Digitized measured value for VCC.
See Table 1.
64 to 65
SRAM
R
Measured MON1
(MSB to LSB)
Digitized measured value for MON1.
See Table 1.
66 to 67
SRAM
R
Measured MON2
(MSB to LSB)
Digitized measured value for MON2.
See Table 1.
68 to 6D
SRAM
R
Reserved
6E
SRAM
Logic states
Bit 7
R
X
HIZSTA
Resistor status bit. A high indicates that both
resistors are in high-impedance mode. A low
indicates that both resistors are operating
normally.
6—
R/W
0HIZCO
Resistor control bit. Setting this bit high
causes both resistors to go into a high-
impedance state.
5—
X
4—
X
3—
X
2—
R
X
TXF
This status bit is high when OUT1 is high
assuming there is an external pullup resistor
on OUT1.
1—
R
X
RXL
This status bit is high when OUT2 is high
assuming there is an external pullup resistor
on OUT2.
0—
RX
RDYB
This status bit goes high when VCC has fallen
below the POA level.
6F
SRAM
Conversion updates
Bit 7
R/W
0
TAU
This bit goes high after a temperature and
address update has occurred for the
corresponding measurement in bytes 60h to
61h. This bit can be written to a 0 by the user
and monitored to verify that a conversion has
occurred.
Main Device (continued)
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