參數(shù)資料
型號: DS1854E-050
廠商: Maxim Integrated Products
文件頁數(shù): 8/22頁
文件大?。?/td> 0K
描述: IC RES TEMP-CNTRL 50/50K 16TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 50 ppm/°C
存儲(chǔ)器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 95°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
DS1854
Dual Temperature-Controlled
Resistors with Two Monitors
16
____________________________________________________________________
MEMORY
LOCATION
EEPROM/
SRAM
R/W
DEFAULT
SETTING
NAME OF
LOCATION
FUNCTION
80
SRAM
R/W
Mode
Bit 7
0
X
6—
—0
X
5—
—0
X
4—
—0
X
3—
—0
X
2—
—0
X
1—
—1
TEN
If TEN = 0, the temperature conversions update and the
resistors can be controlled manually. The user sets the
resistor in manual mode by writing to addresses 82h and
83h in Table 01 to control resistors 0 and 1, respectively.
0—
—1
AEN
AEN = 0 provides manual control of the temperature
index.
81
SRAM
R
Temp index
This byte is the temperature-calculated index used to
select the address of resistor settings in the look-up
tables.
82
SRAM
R/W
00
Resistor 0
Resistor 0 position values from 00h to FFh.
83
SRAM
R/W
00
Resistor 1
Resistor 1 position values from 00h to FFh.
84 to 87
SRAM
00
Reserved
88
EEPROM
R/W
Interrupt enable
This byte configures a maskable interrupt, determining
which event asserts a buffer 1 output (MINT set to 1, see
register 89h in Table 01). If any combination of
temperature, VCC, MON1, or MON2 is desired to generate
an interrupt, the corresponding bits are set to 1. If
interrupt generation is not desired, set all bits to 0.
Bit 7
1
TMP
6—
—1
VCC
5—
—1
MON1
4—
—1
MON2
3—
—0
X
2—
—0
X
1—
—0
X
0—
—0
X
89
EEPROM
R/W
Configuration
Bit 7
0
X
6—
—0
X
Table 01h
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