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參數(shù)資料
型號(hào): DS1856E-M50+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 16/31頁(yè)
文件大?。?/td> 0K
描述: IC DGTL POT 50K 256TAPS 16TSSOP
產(chǎn)品培訓(xùn)模塊: Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 50 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 2 線串口
電源電壓: 2.85 V ~ 5.5 V
工作溫度: -40°C ~ 95°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
Maxim Integrated
23
DS1856
Config
1
Int Enable.................. <R-pw2/W-pw2><NV><F8h> Configures the maskable interrupt for
the Out1 pin.
a)
Temp Enable...... Temperature measurements, outside of the threshold limits, are enabled
to create an active interrupt on the Out1 pin.
b)
VCC Enable......... VCC measurements, outside of the threshold limits, are enabled to create
an active interrupt on the Out1 pin.
c)
MON1 Enable.... MON1 measurements, outside of the threshold limits, are enabled to
create an active interrupt on the Out1 pin.
d)
MON2 Enable.... MON2 measurements, outside of the threshold limits, are enabled to
create an active interrupt on the Out1 pin.
e) MON3 Enable.... MON3 measurements, outside of the threshold limits, are enabled to
create an active interrupt on the Out1 pin.
f)
Reserved ............ EE.
Config........................ <R-pw2/W-pw2><NV><00h> Configure the memory location and the
polarity of the digital outputs.
a)
Reserved ............ EE.
b)
ADEN ................ Auxiliary Device ENable. 128 bytes of EE are addressable depending
on the value of this bit. When set to a 1, the memory is located in or as
Table 01h. When set to a 0, the memory is addressed by using a Device
address of A0h and the locations in memory are 00h to 7Fh.
c)
ADFIX ............... Device Fixable Address. When this bit is set to a 1, the main memory
of the DS1856 is a Device Address equal to the value found in byte
chip_address. When this bit is set to a 0 the main memory of the DS1856
is a Device Address of A2h.
d)
Inv1 .................... Enable the inversion of the relationship between IN1 and OUT1.
e)
Inv2 .................... Enable the inversion of the relationship between IN2 and OUT2.
Chip Address............. This value becomes the Device address for the main memory when
ADFIX bit is set.
Right Shift1 ................ Allows for right-shifting the final answer of some voltage
measurements. This allows for scaling the measurements to the smallest
full-scale voltage and then right-shifting the final result so the reading is
weighted to the correct lsb.
Right Shift0 ................ Allows for right-shifting the final answer of some voltage
measurements. This allows for scaling the measurements to the smallest
full-scale voltage and then right-shifting the final result so the reading is
weighted to the correct lsb.
Res1 ........................... <R-pw2><W-pw2+TENb><FFh> The base value used for Resistor 1
and recalled from Table 5 at the memory address found in T Index.
This register is updated at the end of the Temperature conversion.
Reserved .................... <R-pw2><W-pw2><00h> SRAM.
Res0 ........................... <R-pw2><W-pw2+TENb><FFh> The base value used for Resistor 0
and recalled from Table 4 at the memory address found in T Index.
This register is updated at the end of the Temperature conversion.
.
Register Descriptions (continued)
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