參數(shù)資料
型號: DS1856E-M50+
廠商: Maxim Integrated Products
文件頁數(shù): 18/31頁
文件大?。?/td> 0K
描述: IC DGTL POT 50K 256TAPS 16TSSOP
產(chǎn)品培訓模塊: Obsolescence Mitigation Program
標準包裝: 96
接片: 256
電阻(歐姆): 50k
電路數(shù): 2
溫度系數(shù): 標準值 50 ppm/°C
存儲器類型: 非易失
接口: 2 線串口
電源電壓: 2.85 V ~ 5.5 V
工作溫度: -40°C ~ 95°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 管件
Dual, Temperature-Controlled Resistors with Inter-
nally Calibrated Monitors and Password Protection
Maxim Integrated
25
DS1856
Programming the Look-up Table (LUT)
The following equation can be used to determine which
resistor position setting, 00h to FFh, should be written in
the LUT to achieve a given resistance at a specific tem-
perature.
R = the resistance desired at the output terminal
C = temperature in degrees Celsius
u, v, w, x1, x0, y, z, and α are calculated values found in
the corresponding look-up tables. The variable x from the
equation above is separated into x1 (the MSB of x) and x0
(the LSB of x). Their addresses and LSB values are given
below. The variable y is assigned a value. All other vari-
ables are unsigned. Resistor 0 variables are found in
Table 04, and Resistor 1 variables are found in Table 05.
When shipped from the factory, all other memory loca-
tions in the LUTs are programmed to FFh.
Table 8. Calibration Constants
Internal Calibration
The DS1856 has two methods for scaling an analog
input to a digital result. The two methods are gain and
offset. Each of the inputs (VCC, MON1, MON2, and
MON3) has a unique register for the gain and the offset
found in Table 03h, 92h to 99h, and A2h to A9h.
To scale the gain and offset of the converter for a spe-
cific input, you must first know the relationship between
the analog input and the expected digital result. The
input that would produce a digital result of all zeros is
the null value (normally this input is GND). The input
that would produce a digital result of all ones is the full-
scale (FS) value. The FS value is also found by multiply-
ing an all-ones digital answer by the weighted LSB
(e.g., since the digital reading is a 16-bit register, let us
assume that the LSB of the lowest weighted bit is
50V, then the FS value is 65,535 x 50V = 3.27675V).
A binary search is used to scale the gain of the con-
verter. This requires forcing two known voltages to the
input pin. It is preferred that one of the forced voltages
is the null input and the other is 90% of FS. Since the
LSB of the least significant bit in the digital reading reg-
ister is known, the expected digital results are also
known for both inputs (null/LSB = CNT1 and 90%FS/
LSB = CNT2).
The user might not directly force a voltage on the input.
Instead they have a circuit that transforms light, fre-
quency, power, or current to a voltage that is the input
to the DS1856. In this situation, the user does not need
to know the relationship of voltage to expected digital
result but instead knows the relationship of light, fre-
quency, power, or current to the expected digital result.
An explanation of the binary search used to scale the
gain is best served with the following example pseudo-
code:
/* Assume that the null input is 0.5V. */
/* In addition, the requirement for LSB is 50V. */
FS = 65535 x 50E-6;
/* 3.27675 */
CNT1 = 0.5 / 50E-6;
/* 10000 */
CNT2 = 0.90 x FS / 50E-6;
/* 58981.5 */
/* Thus the null input 0.5V and the 90% of FS input is
2.949075V. */
Set the trim-offset-register to zero;
Set Right-Shift register to zero (typically zero.
See the
Right-Shifting section);
gain_result = 0h;
Clamp = FFF8h/2^(Right_Shift_Register);
For n = 15 down to 0
begin
pos
R C
Ru x
v x C
w x C
xx
y x C
z x C
α,
α
,
()=
+
()+
()
()
+
()+
()
125
25
125
25
2
ADDRESS
VARIABLE
LSB
F8h
u
20
F9h
v
20E-6
FAh
w
100E-9
FBh
x1
21
FCh
x0
2-7
2E-6 (signed)
8E-6 (signed) for -025 version
FDh
y
4E-6 (signed) for -030 version
FEh
z
10E-9
FFh
α
2-2
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