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參數(shù)資料
| 型號： | DS1859B-050+T&R/B |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RES DUAL TEMP-CTRL 16-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 50 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.85 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-LBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 16-CSBGA（4x4） |
| 包裝： | 帶卷 (TR) |
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DS1859
Dual, Temperature-Controlled Resistors with
Internally Calibrated Monitors
24
____________________________________________________________________
Main Device address. The control of write privileges
through the Auxiliary Device address depends on the
value of APEN. Care should be taken with the setting of
MPEN, once set to a 1, assuming WPEN is high.
Access through the Main Device is thereafter denied
unless WPEN is taken to a low level. By this means,
inadvertent end-user write access can be denied.
Main Device address space 60h to 7Fh is SRAM and is
not write protected by APEN, MPEN, or WPEN. For
example, the user may reset flags set by the device.
Note that in single device mode (ADEN bit = 1), APEN
determines the protection level of Table 00, indepen-
dent of WPEN.
The write-protect operation, for both Main and Auxiliary
Devices, is summarized in Tables 6 and 7.
Temperature Conversion
The direct-to-digital temperature sensor measures tem-
perature through the use of an on-chip temperature
measurement technique with an operating range from
-40°C to +102°C. Temperature conversions are initiated
upon power-up, and the most recent conversion is
stored in memory locations 60h and 61h of the Main
Device, which are updated every tframe. Temperature
conversions do not occur during an active read or write
to memory.
The value of each resistor is determined by the tempera-
ture-addressed look-up table. The look-up table assigns
a unique value to each resistor for every 2°C increment
with a 1°C hysteresis at a temperature transition over the
operating temperature range (see Figure 4).
Power-Up and Low-Voltage Operation
During power-up, the device is inactive until VCC
exceeds the digital power-on-reset voltage (POD). At this
voltage, the digital circuitry, which includes the 2-wire
interface, becomes functional. However, EEPROM-
backed registers/settings cannot be internally read
(recalled into shadow SRAM) until VCC exceeds the ana-
log power-on-reset voltage (POA), at which time the
remainder of the device becomes fully functional. Once
VCC exceeds POA, the RDYB bit in byte 6Eh of the Main
Device memory is timed to go from a 1 to a 0 and indi-
cates when analog-to-digital conversions begin. If VCC
ever dips below POA, the RDYB bit reads as a 1 again.
Once a device exceeds POA and the EEPROM is
recalled, the values remain active (recalled) until VCC falls
below POD.
For 2-wire device addresses sourced from EEPROM
(ADFIX = 1), the device address defaults to A2h until VCC
exceeds POA and the EEPROM values are recalled. The
Auxiliary Device (A0h) is always available within this volt-
age window (between POD and the EEPROM recall)
regardless of the programmed state of ADEN.
Furthermore, as the device powers up, the VCClo alarm
flag (bit 4 of 70h in Main Device) defaults to a 1 until the
first VCC analog-to-digital conversion occurs and sets or
clears the flag accordingly.
2-Wire Operation
Clock and Data Transitions: The SDA pin is normally
pulled high with an external resistor or device. Data on
the SDA pin may only change during SCL-low time
periods. Data changes during SCL-high periods will
indicate a START or STOP condition depending on the
conditions discussed below. See the timing diagrams
in Figures 5 and 6 for further details.
START Condition: A high-to-low transition of SDA with
SCL high is a START condition that must precede any
other command. See the timing diagrams in Figures 5
and 6 for further details.
STOP Condition: A low-to-high transition of SDA with
SCL high is a STOP condition. After a read or write
sequence, the stop command places the DS1859 into a
low-power mode. See the timing diagrams in Figures 5
and 6 for further details.
Acknowledge: All address and data bytes are trans-
mitted through a serial protocol. The DS1859 pulls the
SDA line low during the ninth clock pulse to acknowl-
edge that it has received each word.
Standby Mode: The DS1859 features a low-power
mode that is automatically enabled after power-on,
after a STOP command, and after the completion of all
internal operations.
Device Addressing: The DS1859 must receive an 8-bit
device address following a START condition to enable
a specific device for a read or write operation. The
address is clocked into this part MSB to LSB. The
address byte consists of either A2h or the value in
Table 01 8Ch for the Main Device or A0h for the
Auxiliary Device, then the R/W bit. This byte must
match the address programmed into Table 01 8Ch or
A0h (for the Auxiliary Device). If a device address
match occurs, this part will output a zero for one clock
cycle as an acknowledge and the corresponding block
of memory is enabled (see the Memory Organization
section). If the R/W bit is high, a read operation is initi-
ated. If the R/W is low, a write operation is initiated (see
the Memory Organization section). If the address does
not match, this part returns to a low-power mode.
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