參數(shù)資料
型號: DS1862AB+T&R
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA25
封裝: 5 X 5 MM, ROHS COMPLIANT, CSBGA-25
文件頁數(shù): 15/42頁
文件大?。?/td> 586K
代理商: DS1862AB+T&R
DS1862A
XFP Laser Control and Digital Diagnostic IC
22
______________________________________________________________________________________
Warning and Alarm Logic Based on
Signal Conditioners
The DS1862A also has flags that are set by certain logical
conditions on signal conditioner (SC) pins: SC-RX-LOL,
SC-RX-LOS, SC-TX-LOS. Similarly, for each latched
signal conditioner flag there are also mask bits that are
capable of preventing the alarm or warning flag from
causing an INTERRUPT pin to assert. Again, flags are
cleared automatically whenever their memory address
is read. See Figure 11 for more detail.
Quick-Trip Logic and FETG
Shutdown Functionality
In addition to alarms and warnings, the DS1862A also
has quick-trip (QT) functionality (sometimes referred to
as fast alarms) that is capable of shutting down the
LASER with the FETG pin in conjunction with shutting
down IMODSET and IBIASSET. IBMD and IBIASSET cur-
rents are measured and are compared with user-
defined trip points to set the quick-trip flags: QT LOW
TX-P, QT HIGH TX-P, and QT HIGH BIAS. These flags
are also capable of being masked to prevent FETG
from being asserted when an out-of-tolerance condition
is detected. FETG is not asserted by setting the TX-D
pin, SOFT TX-D, or P-DOWN/RST pin to a high state,
however, IMODSET, and IBIASSET will shut down. See
Figure 12 for more detail.
The polarity of the FETG pin can also be reversed by
setting the FETG_POL bit. Once a safety fault has
occurred, the FETG pin and all of the attendant flags
SIGNAL CONDITIONER AND MISCELLANEOUS LOGIC
ANY FLAG
ANY MASK BIT
HIGH TX-P
LOW TX-P
LATCHED-TX-FAULT
HIGH BIAS
INTERRUPT (PIN)
TIMER
LA
TCH
SC-RX-LOS
(PIN)
LATCHED-RX-NR
SC-RX-LOL
(PIN)
LA
TCH
SC-TX-LOS
(PIN)
LATCHED-TX-NR
LATCHED-TX-FAULT
LA
TCH
P-DOWN/RST
(PIN)
LATCHED-RESET-DONE
LATCHED
RX-CDR-NL
LA
TCH
LA
TCH
SC-RX-LOL
(PIN)
LATCHED-
RX-LOS
RX-LOS (PIN)
*
LA
TCH
SC-RX-LOS
(PIN)
SC-RX-LOL (PIN)
TX-FAULT
LATCHED-
MOD-NR
VCC2-FAULT
*
*OPEN DRAIN
MOD-NR (PIN)
LA
TCH
Figure 11. Signal Conditioner and Other Logic
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