
DS1862A
XFP Laser Control and Digital Diagnostic IC
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31
Bit 0: DATA-NR. Bit is high until DS1862A has achieved power-up. Bit goes low, signaling that monitor channel
data is ready to be read.
Bit 1: RX-LOS. Indicates optical loss of the signal and is updated within tLOS-ON.
Bit 2: INTERRUPT. Indicates the state of the INTERRUPT pin and is updated within tINIT_ON.
Bit 3: SOFT P-DOWN/RST. Read/Write bit that places the DS1862A in power-down mode. Toggle to reset. Masked
by Bit 5 of Byte DDh in Table 01h.
Bit 4: P-DOWN/RST. Indicates the digital state of the P-DOWN/RST pin and is updated within tPDR-ON.
Bit 5: MOD-NR State. Indicates the state of MOD-NR pin and is updated within tPDR-ON.
Bit 6: SOFT TX-D. Read/Write bit that disables (shuts down) IBIASSET and IMODSET. Masked by Bit 6 of Byte DDh in Table 01h.
Bit 7: TX-D. Indicates the digital state of the TX-D pin and is updated within tOFF.
6Fh
GCS0 ...............................<R-all/W-all><Status><xx> These are nonlatched flags, indicating the real-time dig-
ital state of a corresponding signal.
Bit 0: Reserved.
Bit 1: Reserved.
Bit 2: Reserved.
Bit 3: RX-CDR-NL not locked. Indicates LOL in Rx path CDR.
Bit 4: RX-NR State. Indicates a NOT READY condition in the Rx path.
Bit 5: Reserved.
Bit 6: TX-F State. Indicates a laser safety fault condition.
Bit 7: TX-NR State. Indicates a NOT READY condition on the Tx path.
74h
POA..................................<R-all/W-all><Volatile><00> A high on bit 7 indicates that VCC3 is below the power-
on analog trip point, POA.
76h
PEC_EN..............................<R-all/W-all><Volatile><00> Bit 0 is used to enable PEC. A value of 1 enables PEC.
77h
→ 7Ah
Host PW Change .............<R-never/W-Host><Shadowed Nonvolatile P><00> This is the 32-bit location that
the DS1862A uses to compare with the PWE to grant host password access. A Read
result is always <FFh>.
7Bh
→ 7Eh
PWE.....................................<R-never/W-all><Volatile><00> This is the 32-bit location that is used to enter the host
and module password to gain access to the DS1862A. A Read result is always <FFh>.
7Fh
Table Select .....................<R-all/W-all><Volatile><01> This is the 8-bit register that controls which section of
upper memory (table) is being addressed by I2C. A value of 00h and 01h results in
addressing Table 01h. Values above 05h are accepted, but do not correspond to
any physical memory.
Table 01h
80h
→ DBh
USER EE ..........................<R-all/W-Module><Nonvolatile><00>
DCh
VCC2/3_SEL......................<R-all/W-Module><Shadowed Nonvolatile><00> Bit 0 of this register controls
whether VCC2 or VCC3 is internally measured by the VCC2/3 monitor channel. A ‘1’
selects VCC2 to be measured.