參數(shù)資料
型號(hào): DS1977-F5
英文描述: 32KB EEPROM iButton
中文描述: 32KB的EEPROM的iButton的
文件頁數(shù): 16/16頁
文件大?。?/td> 102K
代理商: DS1977-F5
Page 16
1/31/03
PARAMETER
Write-1 Low Time (Note
11) (system requirement)
SYMBOL
t
W1L
CONDITIONS
MIN
5
TYP
MAX
15 -
ε
UNITS
μs
Standard Speed
Overdrive Speed
1
2 -
ε
μs
IO pin, 1-Wire Read
Read Low Time (Note
12) (system requirement)
t
RL
Standard Speed
5
15 -
δ
μs
Overdrive Speed
Standard Speed, V
PUP
> 4.5V.
Standard Speed
Overdrive Speed
Standard Speed, V
PUP
> 4.5V.
1
2 -
δ
54
60
6
20
μs
μs
μs
μs
μs
Read-0 Low
(data from slave)
t
SPD
20
15
2
Read Sample Time (Note
12)
(system requirement)
t
MSR
t
RL
+
δ
Standard Speed
Overdrive Speed
t
RL
+
δ
t
RL
+
δ
15
2
μs
μs
VCC Output
IO to VCC Voltage Drop
(Note 13)
Load current
V
IOCC
7 mA load current,
V
IO
= 2.8V
V
CC
= 2.7 to 5.25V
0.1
V
I
LOAD
7
mA
Note 1:
Note 2:
This is a requirement that the 1-Wire master has to meet.
Maximum allowable pull-up resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only
one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pull-up such as that found in the DS2480B may be required.
V
TL
, V
TH
are a function of the internal supply voltage.
Voltage below which, during a falling edge on IO, a logic '0' is detected.
The voltage on IO needs to be less or equal to V
ILMAX
whenever the master drives the line
low.
Voltage above which, during a rising edge on IO, a logic '1' is detected.
After V
TH
is crossed during a rising edge on IO, the voltage on IO has to drop by V
HY
to be
detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been reached
before.
Interval during the negative edge on IO at the beginning of a Presence Detect pulse
between the time at which the voltage is 90% of V
PUP
and the time at which the voltage is
10% of V
PUP
.
ε
represents the time required for the pull-up circuitry to pull the voltage on IO up from V
IL
to V
TH
.
δ
represents the time required for the pull-up circuitry to pull the voltage on IO up from V
IL
to the input high threshold of the bus master.
At 7mA load, V
CC
must not be less than
2.7V
, regardless of V
IO
. If this condition cannot be
met, increase the minimum V
PUP
to 3.0V or higher.
The strong pull-up must be on when the t
DCSA
interval elapses. The t
DCSA
value must be
determined in design as the maximum time required to turn the bypass NCH transistor fully
on.
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 16
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