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參數(shù)資料
| 型號(hào)： | DS1977-F5 |
| 英文描述： | 32KB EEPROM iButton |
| 中文描述： | 32KB的EEPROM的iButton的 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 102K |
| 代理商： | DS1977-F5 |
Page 4
1/31/03
Version Register (DS1977)
ADDR
b7
N/A
VER2
b6
b5
b4
0
b3
0
b2
0
b1
0
b0
0
VER1
VER0
Bit Description
VER: Chip Revision
Indicator
Bit(s)
b5 to
b7
Definition
These hard-wired bits are used to distinguish different
revisions or chips that use the same 1-Wire family code
as the DS1977. The initial version of the DS1977 chip will
have all revision bits set to 0.
Figure 4. ADDRESS REGISTERS
TARGET ADDRESS (TA1)
T7
T6
T5
T4
T3
T2
T1
T0
TARGET ADDRESS (TA2)
T15
T14
T13
T12
T11
T10
T9
T8
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
AA
PF
E5
E4
E3
E2
E1
E0
Address Registers and Transfer Status
Because of the serial data transfer, the DS1977 iButton employs three address registers, called
TA1, TA2 and E/S (Figure ). Registers TA1 and TA2 must be loaded with the target address to
which the data will be written or from which data will be sent to the 1-Wire master upon a Read
command. Register E/S acts like a byte counter and Transfer Status register. It is used to verify
data integrity with write commands. Therefore, the 1-Wire master only has read access to this
register. The lower six bits of the E/S register indicate the address of the last byte that has been
written to the scratchpad. This address is called Ending Offset. Bit 6 of the E/S register, called PF,
is set if the number of data bits sent by the 1-Wire master is not an integer multiple of 8 or if the
data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad will clear
the PF bit. Note that the lowest six bits of the target address also determine the address within the
scratchpad, where intermediate storage of data will begin. This address is called byte offset. If the
target address (TA1) for a Write command is 103Ch for example, then the scratchpad will store
incoming data beginning at the byte offset 3Ch and will be full after only four bytes. The
corresponding ending offset in this example is 3Fh. For best economy of speed and efficiency, the
target address for writing should point to the beginning of a new page, i.e., the byte offset will be
0. Thus the full 64-byte capacity of the scratchpad is available, resulting also in the ending offset
of 3Fh. However, it is possible to write one or several contiguous bytes somewhere within a page.
The ending offset together with the Partial Flag support the 1-Wire master checking the data
integrity after a Write command. The highest valued bit of the E/S register, called AA is valid only
if the PF flag reads 0. If PF is 0 and AA is 1, a copy has taken place. The AA bit is cleared when
the device receives a write scratchpad command.
相關(guān)PDF資料 |
PDF描述 |
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| DS1982U | UniqueWare iButton |
| DS1985U | UniqueWare iButton |
| DS1986 | 64 kbit Add-Only iButton |
| DS1986-F3 | EPROM|256X32X8|BUTTON|METAL |
| DS1986F5 | EPROM|256X32X8|BUTTON|METAL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1977-F5- | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Password-Protected 32KB EEPROM iButton |
| DS1977-F5# | 功能描述:iButton Password-Protected 32KB EEPROM iButton RoHS:否 存儲(chǔ)類型:SRAM 存儲(chǔ)容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1977-F5+ | 功能描述:iButton RoHS:否 存儲(chǔ)類型:SRAM 存儲(chǔ)容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1981U-F3-1125+ | 功能描述:iButton RoHS:否 存儲(chǔ)類型:SRAM 存儲(chǔ)容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1981U-F3-114C+ | 功能描述:iButton RoHS:否 存儲(chǔ)類型:SRAM 存儲(chǔ)容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
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