參數資料
型號: DS21348TN
廠商: Maxim Integrated Products
文件頁數: 36/76頁
文件大小: 0K
描述: IC LIU LN T1/E1/J1 3.3V 44-TQFP
產品培訓模塊: Lead (SnPb) Finish for COTS
產品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 160
類型: 線路接口裝置(LIU)
驅動器/接收器數: 1/1
規(guī)程: T1/E1/J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應商設備封裝: 44-TQFP(10x10)
包裝: 托盤
DS21348/DS21Q348
41 of 76
6. DIAGNOSTICS
6.1 In-Band Loop Code Generation and Detection
The DS21348 can generate and detect a repeating bit pattern that is from one to eight or sixteen bits in
length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition
(TCD1 and TCD2) registers and select the proper length of the pattern by setting the TC0 and TC1 bits in
the In-Band Code Control (IBCC) register. When generating a 1, 2, 4, 8, or 16 bit pattern both the
transmit code registers (TCD1 and TCD2) must be filled with the proper code. Generation of a 1, 3, 5, or
7-bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern will be transmitted as
long as the TLCE control bit (CCR3.3) is enabled. As an example, if the user wished to transmit the
standard “l(fā)oop up” code for Channel Service Units which is a repeating pattern of ...10000100001... then
80h would be loaded into TCD1 and the length would set using TC1 and TC0 in the IBCC register to 5
bits.
The DS21348 can detect two separate repeating patterns to allow for both a “l(fā)oop up” code and a “l(fā)oop
down” code to be detected. The user will program the codes to be detected in the Receive Up Code
Definition (RUPCD1 and RUPCD2) registers and the Receive Down Code Definition (RDNCD1 and
RDNCD2) registers and the length of each pattern will be selected via the IBCC register. The DS21348
will detect repeating pattern codes with bit error rates as high as 1x10-2. The code detector has a nominal
integration period of 48ms, hence, after about 48ms of receiving either code, the proper status bit (LUP at
SR.7 and LDN at SR.6) will be set to a one. Normally codes are sent for a period of 5 seconds. It is
recommended that the software poll the DS21348 every 100ms to 1000ms until 5 seconds has elapsed to
insure that the code is continuously present.
IBCC (0AH): IN-BAND CODE CONTROL REGISTER
(MSB)
(LSB)
TC1
TC0
RUP2
RUP1
RUP0
RDN2
RDN1
RDN0
SYMBOL
POSITION
DESCRIPTION
TC1
IBCC.7
Transmit Code Length Definition Bit 1. See Table 6-1.
TC0
IBCC.6
Transmit Code Length Definition Bit 0. See Table 6-1.
RUP2
IBCC.5
Receive Up Code Length Definition Bit 2. See Table 6-2.
RUP1
IBCC.4
Receive Up Code Length Definition Bit 1. See Table 6-2.
RUP0
IBCC.3
Receive Up Code Length Definition Bit 0. See Table 6-2.
RDN2
IBCC.2
Receive Down Code Length Definition Bit 2. See Table 6-2.
RDN1
IBCC.1
Receive Down Code Length Definition Bit 1. See Table 6-2.
RDN0
IBCC.0
Receive Down Code Length Definition Bit 0. See Table 6-2.
Table 6-1. Transmit Code Length
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