參數(shù)資料
型號: DS2143N
廠商: Maxim Integrated Products
文件頁數(shù): 21/44頁
文件大?。?/td> 0K
描述: IC CONTROLLER E1 5V LP 40-DIP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 10
控制器類型: E1 控制器
接口: 并行/串行
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 10mA
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-PDIP
包裝: 管件
DS2143/DS2143Q
28 of 44
11.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
The DS2143 provides for access to both the Additional (Sa) and International (Si) bits. On the receive
side, the RAF and RNAF registers will always report the data as it received in the Additional and
International bit locations. The RAF and RNAF registers are updated with the setting of the Receive
Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the
RAF and RNAF registers. It has 250
s to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250
s to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if either the DS2143 is programmed: (1) to source the Si bits
from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa
bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits is set to 1. Please see the register
descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram in Section 13 for more details.
RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)
(MSB)
(LSB)
Si
00110
1
SYMBOL
POSITION
NAME AND DESCRIPTION
Si
RAF.7
International Bit.
0
RAF.6
Frame Alignment Signal Bit.
0
RAF.5
Frame Alignment Signal Bit.
1
RAF.4
Frame Alignment Signal Bit.
1
RAF.3
Frame Alignment Signal Bit.
0
RAF.2
Frame Alignment Signal Bit.
1
RAF.1
Frame Alignment Signal Bit.
1
RAF.0
Frame Alignment Signal Bit.
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