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參數(shù)資料
| 型號： | DS2149Q+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1 5V 28-PLCC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 500 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1/J1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
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DS2149
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In software mode, the device can generate an interrupt to indicate that the QRSS pattern synchronization
has been declared or lost. Clearing the QRSS bit in the interrupt mask register enables the interrupt. Use
the QPD output to increment an external bit error counter and use the interrupt to reset the counter. The
QRSS bit in the status register is set when the QRSS pattern is detected and cleared when pattern is lost
(more than 6 bit errors in a window of 64 bits). The QRSS bit in the transition status register indicates
that the QRSS status has changed since the last QRSS interrupt clear command.
10.2.3 In-Band Network Loop-Up or Loop-Down Code Generator
In-band network loop-up or loop-down transmission is available in software mode only. The loop-up
code is transmitted when PAT0 = 1 and PAT1 = 0 in CR2. Logic errors and bipolar violations can still be
inserted when loop codes are being transmitted.
10.3Error Insertion and Detection
10.3.1 Bipolar Violation Insertion (INSBPV)
INSBPV is available in NRZ mode. Sampling occurs on the falling edge of TCLK. A rising edge on the
NSBPV pin inserts a BPV on the next available mark, except in the following conditions:
1) If the BPV would violate a B8ZS codeword.
2) When LLB and TAIS are both active. In this case, the BPV is looped back to the BPV pin and the line
driver transmits all ones with no violation.
3) When RLB is active.
4) When NLOOP is active.
BPVs can be inserted in both NRZ and bipolar data modes when the DS2149 is configured to transmit
internally generated data patterns (QRSS or in-band loop codes).
10.3.2 Logic Error Insertion (INSLE)
When transmitting QRSS or in-band loop codes, a logic error is inserted into the outbound data pattern on
a rising edge of the INSLER pin. Remember, when transmitting the QRSS pattern, logic error insertion is
inhibited if the error would replace a 1 with a 0 and result in a string of 15 or more consecutive 0s.
10.3.3 Logic Error Detection (QPD)
After QRSS pattern synchronization, logic errors are reported at the QPD output pin. If a logic error
occurs, the QPD pin goes high for one-half RCLK cycle. In software mode, the CLKE pin determines the
phase relationship between QPD and RCLK. When CLKE is low, QPD is high when RCLK is high.
When CLKE is high, QPD is high when RCLK is low. To count logic errors, use the QPD output to
increment an external error counter. A continuous output high indicates loss of synchronization to the
QRSS pattern or receive-carrier loss.
10.3.4 Bipolar Violation Detection (BPV)
When the B8ZS encoders and decoders are disabled or when configured for NRZ mode, bipolar
violations are reported at the BPV output pin. BPV goes high for a full clock cycle to indicate a bipolar
violation. When the B8ZS encoders and decoders are enabled, BPVs that are not part of codewords are
not reported.
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