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參數(shù)資料
| 型號(hào)： | DS2149Q+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1 5V 28-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1/J1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
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DS2149
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5. TRANSMITTER
5.1 Transmit Digital Data Interface
Data is clocked into the device at the TCLK rate. In bipolar mode, TPOS and TNEG are the data inputs;
in NRZ mode, TDATA is the data input. Input data can pass through either the jitter attenuator or the
B8ZS encoder or both. In software mode, setting ENCENB enables B8ZS encoding. In hardware mode,
floating the MODE1 pin enables B8ZS encoding. With B8ZS encoding enabled, the L0 through L3 inputs
determine the coding and is listed in Table 4-E. TCLK supplies input synchronization. See Section 12 for
the TCLK and MCLK timing requirements.
5.2 Transmit Monitoring
In software mode, the DFMO bit in the status register is set when an open circuit in the transmitter path is
detected. A transition on this bit can provide an interrupt, and a transition sets the DFMO bit in the
transition status register. Setting CDFMO in the interrupt mask register, leaving a 1 in that bit location
masks the interrupt.
5.3 Transmit Idle Mode
Transmit idle mode allows multiple transceivers to be connected to a single line for redundant
applications. When TCLK is not present, transmit idle mode becomes active, and TTIP and TRING
change to high-impedance state. Remote loopback, dual loopback, TAIS, or detection of network loop-up
code in the receive direction temporarily disable the high-impedance state.
5.4 Transmit Pulse Shape
As shown in Table 4-E, line build-out control inputs (L0 through L3) determine the transmit pulse shape.
In software mode, these control inputs are located in control register 1; in hardware mode, these control
inputs are the L0 through L3 pins.
Shaped pulses meeting the various T1, DS1, and DSX-1 specifications are applied to the AMI line driver
for transmission onto the line at TTIP and TRING. The transceiver produces DSX-1 pulses for short-haul
T1 applications (settings from 0dB to 6dB of cable) and DS1 pulses for long-haul T1 applications
(settings from 0dB to -22.5dB). Refer to Table 4-E for pulse mask specifications.
6. RECEIVER
A 1:1 transformer provides the interface between the twisted pair and receiver inputs RTIP and RRING.
Recovered data is output at RPOS and RNEG (or RDATA in NRZ mode), and the recovered clock is
output at RCLK. See Section 12 for receiver timing specifications.
6.1 Receive Equalizer
The receiver can apply up to 36dB of gain. Control of the equalizer is accomplished by the L0 through L3
control inputs. These control signals are detailed in Table 4-E and determine the maximum gain that is
applied. In software mode, these control signals are in Control Register 1; in hardware mode, these
control inputs are the L0 through L3 pins. With L0 low, up to 36dB of gain can be applied; when L0 is
high, 26dB can be applied in the gain limit to provide better noise immunity in shorter loop operations.
6.2 Receive Data Recovery
The clock and data recovery engine provides input jitter tolerance that exceeds the requirements of AT&T
62411. Inbound signal is filtered, equalized, and over-sampled 16 times. Then it is applied to the B8ZS
decoder if enabled.
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