參數(shù)資料
型號(hào): DS2154L
廠商: Maxim Integrated Products
文件頁數(shù): 15/87頁
文件大小: 0K
描述: IC TXRX E1 1CHIP 5V ENH 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 管件
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2154
22 of 87
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
SYMBOL
POSITION
NAME AND DESCRIPTION
Sa8S
RCR2.7
Sa8 Bit Select. Set to 1 to have RLCLK pulse at the Sa8 bit
position; set to 0 to force RLCLK low during Sa8 bit position.
See Section 14 for timing details.
Sa7S
RCR2.6
Sa7 Bit Select. Set to 1 to have RLCLK pulse at the Sa7 bit
position; set to 0 to force RLCLK low during Sa7 bit position.
See Section 14 for timing details.
Sa6S
RCR2.5
Sa6 Bit Select. Set to 1 to have RLCLK pulse at the Sa6 bit
position; set to 0 to force RLCLK low during Sa6 bit position.
See Section 14 for timing details.
Sa5S
RCR2.4
Sa5 Bit Select. Set to 1 to have RLCLK pulse at the Sa5 bit
position; set to 0 to force RLCLK low during Sa5 bit position.
See Section 14 for timing details.
Sa4S
RCR2.3
Sa4 Bit Select. Set to 1 to have RLCLK pulse at the Sa4 bit
position; set to 0 to force RLCLK low during Sa4 bit position.
See Section 14 for timing details.
RBCS
RCR2.2
Receive Side Backplane Clock Select.
0 = if RSYSCLK is 1.544MHz
1 = if RSYSCLK is 2.048MHz
RESE
RCR2.1
Receive Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
RCR2.0
Not Assigned. Should be set to 0 when written.
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