參數(shù)資料
型號: DS2154L
廠商: Maxim Integrated Products
文件頁數(shù): 6/87頁
文件大?。?/td> 0K
描述: IC TXRX E1 1CHIP 5V ENH 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 90
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 管件
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2154
14 of 87
2.4 Line Interface Pins
PIN
NAME
FUNCTION
21
MCLK
Master Clock Input. A 2.048MHz (±50ppm) clock source with TTL levels is applied at
this pin. This clock is used internally for both clock/data recovery and for jitter
attenuation. A quartz crystal of 2.048MHz may be applied across MCLK and XTALD
instead of the TTL level clock source.
22
XTALD
Quartz Crystal Driver. A quartz crystal of 2.048MHz may be applied across MCLK
and XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a
TTL clock source is applied at MCLK.
13
8XCLK
Eight Times Clock. A 16.384MHz clock that is frequency locked to the 2.048MHz
clock provided from the clock/data recovery block (if the jitter attenuator is enabled on
the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit
side). Can be internally disabled via the TEST2 register if not needed.
12
LIUC
Line Interface Connect. Tie low to separate the line interface circuitry from the
framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/
RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter
circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When
LIUC is tied high, the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be
tied low.
16, 17
RTIP,
RRING
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect
via a 1:1 transformer to the E1 line. See Section 13 for details.
29, 32
TTIP,
TRING
Transmit Tip and Ring. Analog line driver outputs. These pins connect via a 1:1.15 or
1:1.36 step-up transformer to the E1 line. See Section 13 for details.
2.5 Supply Pins
PIN
NAME
FUNCTION
44, 61,
81, 83
DVDD
Digital Positive Supply. 5.0V ±5%. Should be tied to the RVDD and TVDD pins.
18
RVDD
Receive Analog Positive Supply. 5.0V ±5%. Should be tied to the DVDD and TVDD
pins.
31
TVDD
Transmit Analog Positive Supply. 5.0V ±5%. Should be tied to the RVDD and DVDD
pins.
45, 60,
80, 84
DVSS
Digital Signal Ground. Should be tied to the RVSS and TVSS pins.
19, 20,
24
RVSS
Receive Analog Signal Ground. 0V. Should be tied to the DVSS and TVSS pins.
30
TVSS
Transmit Analog Ground. 0V. Should be tied to the RVSS and DVSS pins.
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