參數(shù)資料
型號: DS21554LN+
廠商: Maxim Integrated Products
文件頁數(shù): 73/124頁
文件大小: 0K
描述: IC TXRX E1 1-CHIP 5V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC,J1,T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: 遠程和 AIS 警報檢測器 / 發(fā)生器
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
52 of 124
7.4.
FAS Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12–bit counter that records word errors in the Frame Alignment Signal in time slot 0. This counter is
disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS
alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS
word error count in a one second period is 4000, this counter cannot saturate.
FASCR1: FAS ERROR COUNT REGISTER 1 (Address = 02 Hex)
FASCR2: FAS ERROR COUNT REGISTER 2 (Address = 04 Hex)
(MSB)
(LSB)
FAS11
FAS10
FAS9
FAS8
FAS7
FAS6
(Note 1)
FASCR1
FAS5
FAS4
FAS3
FAS2
FAS1
FAS0
(Note 2)
FASCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
FAS11
FASCR1.7
MSB of the 12-Bit FAS Error Count
FAS0
FASCR2.2
LSB of the 12-Bit FAS Error Count
Note 1: The lower two bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-Bit counter.
Note 2: The lower two bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error counter.
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