參數(shù)資料
型號(hào): DS2172
英文描述: Bit Error Rate Tester BERT
中文描述: 位誤碼率測(cè)試器(BERT)
文件頁(yè)數(shù): 11/21頁(yè)
文件大?。?/td> 213K
代理商: DS2172
DS2172
11 of 21
NOTES FOR TABLES 4 AND 5:
1.
PTR = Polynomial Tap Register (address = 05)
2.
PLR = Pattern Length Register (address = 04)
3.
PSR3 = Pattern Set Register 3 (address = 00)
4.
PSR2 = Pattern Set Register 2 (address = 01)
5.
PSR1 = Pattern Set Register 1 (address = 02)
6.
PSR0 = Pattern Set Register 0 (address = 03)
7.
TINV = Transmit Data Inversion Select Bit (EIR.5)
8.
RINV = Receive Data Inversion Select Bit (EIR.4)
9.
For the 2
32
-1 pattern, the random pattern actually repeats every (4093 x 2
20
) + 1046529 bits instead of
2
32
- 1.
8.0 BIT COUNT REGISTERS
The Bit Count Registers (BCR3 to BCR0) comprise a 32-bit count of bits (actually RCLK cycles)
received at RDATA. BC31 is the MSB of the 32-bit count. The bit counter increments for each cycle of
RCLK when input pin RDIS is low. The bit counter is disabled during loss of SYNC. The Status Register
bit BCOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear the
BCR by either toggling the LC bit or pin. The DS2172 latches the bit count into the BCR registers and
clears the internal bit count when either the PCR.4 bit or the LC input pin toggles from low to high. The
bit count and bit error count (available via the BECRs) are used by an external processor to compute the
BER performance on a loop or channel basis.
BIT COUNT REGISTERS
(MSB) (LSB)
BC31
BC30
BC29
BC28
BC23
BC22
BC21
BC20
BC15
BC14
BC13
BC12
BC7
BC6
BC5
BC4
BC27
BC19
BC11
BC3
BC26
BC18
BC10
BC2
BC25
BC17
BC9
BC1
BC24
BC16
BC8
BC0
BCR3 (addr.=08 Hex)
BCR2 (addr.=09 Hex)
BCR1 (addr.=0A Hex)
BCR0 (addr.=0B Hex)
9.0 BIT ERROR COUNT REGISTERS
The Bit Error Count Registers (BECR3 to BECR0) comprise a 32-bit count of bits received in error at
RDATA. The bit error counter is disabled during loss of SYNC. BEC31 is the MSB of the 32-bit count.
The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition,
the user must clear the BECR by either toggling the LC bit or pin. The DS2172 latches the bit error count
into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC input
pin toggles from low to high. The bit count (available via the BCRs) and bit error count are used by an
external processor to compute the BER performance on a loop or channel basis.
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