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參數資料
| 型號： | DS2172T |
| 英文描述： | Bit Error Rate Tester BERT |
| 中文描述： | 誤碼率測試儀誤碼 |
| 文件頁數： | 12/21頁 |
| 文件大?。?/td> | 213K |
| 代理商： | DS2172T |
DS2172
12 of 21
BIT ERROR COUNT REGISTERS
(MSB) (LSB)
BEC31
BEC30
BEC29
BEC28
BEC27
BEC26
BEC25
BEC24
BECR3
(addr.=0C Hex)
BECR2
(addr.=0D Hex)
BECR1
(addr.=0E Hex)
BECR0
(addr.=0F Hex)
BEC23
BEC22
BEC21
BEC20
BEC19
BEC18
BEC17
BEC16
BEC15
BEC14
BEC13
BEC12
BEC11
BEC10
BEC9
BEC8
BEC7
BEC6
BEC5
BEC4
BEC3
BEC2
BEC1
BEC0
10.0 PATTERN RECEIVE REGISTERS
The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The
operation of these registers depends on the synchronization status of the DS2172. Asserting the RL bit
(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received
at RDATA into the PRR registers. When the DS2172 is in sync (SR.0 = 1) asserting RL will latch the
pattern that to which the device has established synchronization. Since the receiver has no knowledge of
the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an
example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,
11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the
PRR registers.
PATTERN RECEIVE REGISTERS
(MSB) (LSB)
PR31
PR30
PR29
PR28
PR23
PR22
PR21
PR20
PR15
PR14
PR13
PR12
PR7
PR6
PR5
PR4
PR27
PR19
PR11
PR3
PR26
PR18
PR10
PR2
PR25
PR17
PR9
PR1
PR24
PR16
PR8
PR0
PRR3 (addr.=10 Hex)
PRR2 (addr.=11 Hex)
PRR1 (addr.=12 Hex)
PRR0 (addr.=13 Hex)
11.0 STATUS REGISTER AND INTERRUPT MASK REGISTER
The Status Register (SR) contains information on the current real time status of the DS2172. When a
particular event has occurred, the appropriate bit in the register will be set to a 1. All of the bits in these
registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a
bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. For the BED, BCOF,
and BECOF status bits, they will be cleared when read and will not be set again until the event has
occurred again. For RLOS, RA0, and RA1 status bits, they will be cleared when read if the condition no
longer persists.
The SR register has the unique ability to initiate a hardware interrupt via the
INT
pin. Each of the alarms
and events in the SR can be either masked or unmasked from the interrupt pins via the Interrupt Mask
Register (IMR).
相關PDF資料 |
PDF描述 |
|---|---|
| DS2172TN | Bit Error Rate Tester BERT |
| DS2172 | Bit Error Rate Tester BERT |
| DS2174DK | Enhanced Bit Error-Rate Tester Design Kit |
| DS2175S | PCM， Other/Special/Miscellaneous |
| DS2175SN | PCM， Other/Special/Miscellaneous |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS2172T/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:IC TESTER BIT ERROR RATE 32-TQFP 制造商:Maxim Integrated Products 功能描述:Telecom ICs Bit Error Rate Tester (BERT) |
| DS2172T/T&R+ | 制造商:Maxim Integrated Products 功能描述:BERT 32P TQFP T&R LEAD FREE - Tape and Reel |
| DS2172T/T&R | 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2172T+ | 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2172T+T&R | 制造商:Maxim Integrated Products 功能描述:BIT ERROR RATE TESTER 32TQFP - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TESTER BIT ERROR RATE 32-TQFP 制造商:Maxim Integrated Products 功能描述:Telecom ICs Bit Error Rate Tester (BERT) |
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