- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376965 > DS2172T Bit Error Rate Tester BERT PDF資料下載
參數(shù)資料
| 型號： | DS2172T |
| 英文描述： | Bit Error Rate Tester BERT |
| 中文描述： | 誤碼率測試儀誤碼 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 213K |
| 代理商： | DS2172T |
DS2172
5 of 21
PIN
24
SYMBOL
RL
TYPE
I
DESCRIPTION
Receive Load.
A positive-going edge loads the previous 32 bits of data
received at RDATA into the Pattern Receive Registers. RL is logically
OR’ed with control bit PCR.3. Should be tied to V
SS
if not used.
Receive Data.
Received NRZ serial data, sampled on the rising edge of
RCLK.
Receive Disable.
Set high to prevent the data at RDATA from being
sampled. Set low to allow bits at RDATA to be sampled. Should be tied
to V
SS
if not used. See Figure 6 for timing information. All receive side
operations are disabled when RDIS is high.
Receive Clock.
Input clock from transmission link. 0 to 52 MHz. Can be
a gapped clock. Fully independent from TCLK.
Positive Supply.
5.0V.
Signal Ground.
0.0V. Should be tied to local ground plane.
Transmit Clock.
Transmit demand clock. 0 to 52 MHz. Can be a gapped
clock. Fully independent of RCLK.
Transmit Disable.
Set high to hold the current bit being transmitted at
TDATA. Set low to allow the next bit to appear at TDATA. Should be
tied to V
SS
if not used. See Figure 7 for timing information. All transmit
side operations are disabled when TDIS is high.
Transmit Data.
Transmit NRZ serial data, updated on the rising edge of
TCLK.
25
RDATA
I
26
RDIS
I
27
RCLK
I
28
29
30
V
DD
V
SS
TCLK
-
-
I
31
TDIS
I
32
TDATA
O
DS2172 REGISTER MAP
Table 2
ADDRESS
R/W
00
R/W
01
R/W
02
R/W
03
R/W
04
R/W
05
R/W
06
R/W
07
R/W
08
R
09
R
0A
R
0B
R
REGISTER NAME
Pattern Set Register 3.
Pattern Set Register 2.
Pattern Set Register 1.
Pattern Set Register 0.
Pattern Length Register.
Polynomial Tap Register.
Pattern Control Register.
Error Insert Register.
Bit Counter Register 3.
Bit Counter Register 2.
Bit Counter Register 1.
Bit Counter Register 0.
ADDRESS
0C
0D
0E
0F
10
11
12
13
14
15
1C
R/W
R
R
R
R
R
R
R
R
R
R/W
R/W
REGISTER NAME
Bit Error Counter Register 3.
Bit Error Counter Register 2.
Bit Error Counter Register 1.
Bit Error Counter Register 0.
Pattern Receive Register 3.
Pattern Receive Register 2.
Pattern Receive Register 1.
Pattern Receive Register 0.
Status Register.
Interrupt Mask Register.
Test Register (see note 1)
NOTE:
1.
The Test Register must be set to 00 hex to insure proper operation of the DS2172.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2172TN | Bit Error Rate Tester BERT |
| DS2172 | Bit Error Rate Tester BERT |
| DS2174DK | Enhanced Bit Error-Rate Tester Design Kit |
| DS2175S | PCM， Other/Special/Miscellaneous |
| DS2175SN | PCM， Other/Special/Miscellaneous |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2172T/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:IC TESTER BIT ERROR RATE 32-TQFP 制造商:Maxim Integrated Products 功能描述:Telecom ICs Bit Error Rate Tester (BERT) |
| DS2172T/T&R+ | 制造商:Maxim Integrated Products 功能描述:BERT 32P TQFP T&R LEAD FREE - Tape and Reel |
| DS2172T/T&R | 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2172T+ | 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2172T+T&R | 制造商:Maxim Integrated Products 功能描述:BIT ERROR RATE TESTER 32TQFP - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TESTER BIT ERROR RATE 32-TQFP 制造商:Maxim Integrated Products 功能描述:Telecom ICs Bit Error Rate Tester (BERT) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。