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參數(shù)資料
| 型號(hào)： | DS2172TN |
| 英文描述： | Bit Error Rate Tester BERT |
| 中文描述： | 誤碼率測(cè)試儀誤碼 |
| 文件頁(yè)數(shù)： | 4/21頁(yè) |
| 文件大?。?/td> | 213K |
| 代理商： | DS2172TN |
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DS2172
4 of 21
DETAILED PIN DESCRIPTION
Table 1
PIN
SYMBOL
TYPE
1
TL
I
DESCRIPTION
Transmit Load.
A positive-going edge loads the pattern generator with
the contents of the Pattern Set Registers. The MSB of the repetitive or
pseudorandom pattern appears at TDATA after the third positive edge of
TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should
be tied to V
SS
if not used. See Figure 8 for timing information.
Data Bus.
An 8-bit multiplexed address/data bus.
Data Bus.
An 8-bit multiplexed address/data bus.
Test.
Set high to 3-state all output pins (
INT
, ADx, TDATA, RLOS).
Should be tied to V
SS
to enable all outputs.
Signal Ground.
0.0V. Should be tied to local ground plane.
Data Bus.
An 8-bit multiplexed address/data bus.
Data Bus.
An 8-bit multiplexed address/data bus.
Data Bus.
An 8-bit multiplexed address/data bus.
Data Bus.
An 8-bit multiplexed address/data bus.
Data Bus.
An 8-bit multiplexed address/data bus.
Data Bus.
An 8-bit multiplexed address/data bus.
Signal Ground.
0.0V. Should be tied to local ground plane.
Positive Supply.
5.0V.
Bus Type Select.
Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the
RD
(DS),
ALE(AS), and
WR
(R/
W
) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Read Input (Data Strobe).
Chip Select.
Must be low to read or write the port.
Address Latch Enable (Address Strobe).
A positive going edge serves
to demultiplex the bus.
Write Input (Read/Write).
Alarm Interrupt.
Flags host controller during conditions defined in
Status Register. Active low, open drain output.
Positive Supply.
5.0V.
Signal Ground.
0.0V. Should be tied to local ground plane.
Load Count.
A positive-going edge latches the current bit and bit error
count into the user accessible BCR and BECR registers and clears the
internal count registers. LC is logically OR’ed with control bit PCR.4.
Should be tied to V
SS
if not used.
Receive Loss Of Sync.
Indicates the real time status of the receive
synchronizer. Active high output.
2
3
4
AD0
AD1
TEST
I/O
I/O
I
5
6
7
8
9
V
SS
AD2
AD3
AD4
AD5
AD6
AD7
V
SS
V
DD
BTS
-
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I
10
11
12
13
14
15
16
17
RD
(DS)
I
I
I
CS
ALE(AS)
18
19
WR
(R/
W
)
I
INT
O
20
21
22
V
DD
V
SS
LC
-
-
I
23
RLOS
O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2172 | Bit Error Rate Tester BERT |
| DS2174DK | Enhanced Bit Error-Rate Tester Design Kit |
| DS2175S | PCM， Other/Special/Miscellaneous |
| DS2175SN | PCM， Other/Special/Miscellaneous |
| DS2176IND | Telecommunication IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2172TN/T&R | 功能描述:電信集成電路 RoHS:否 制造商:STMicroelectronics 類(lèi)型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2172TN+ | 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類(lèi)型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2172TN+T&R | 制造商:Maxim Integrated Products 功能描述:BERT 32P TQFP T&R IND LEAD FREE - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC BIT ERROR RATE TESTER 32TQFP 制造商:Maxim Integrated Products 功能描述:Telecom ICs Bit Error Rate Tester (BERT) |
| DS2172TN+T&R | 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類(lèi)型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| DS2174 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:EBERT |
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