參數(shù)資料
型號： DS2172TN
廠商： DALLAS SEMICONDUCTOR
元件分類： Telecom IC:Other
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP32
封裝： TQFP-32
文件頁數(shù)： 18/22頁
文件大?。?/td> 174K
代理商： DS2172TN
DS2172
5 of 22
PIN
SYMBOL
TYPE
DESCRIPTION
24
RL
I
Receive Load. A positive-going edge loads the previous 32 bits of data
received at RDATA into the Pattern Receive Registers. RL is logically
OR’ed with control bit PCR.3. Should be tied to VSS if not used.
25
RDATA
I
Receive Data. Received NRZ serial data, sampled on the rising edge of
RCLK.
26
RDIS
I
Receive Disable. Set high to prevent the data at RDATA from being
sampled. Set low to allow bits at RDATA to be sampled. Should be tied
to VSS if not used. See Figure 6 for timing information. All receive side
operations are disabled when RDIS is high.
27
RCLK
I
Receive Clock. Input clock from transmission link. 0 to 52 MHz. Can be
a gapped clock. Fully independent from TCLK.
28
VDD
-
Positive Supply. 5.0V.
29
VSS
-
Signal Ground. 0.0V. Should be tied to local ground plane.
30
TCLK
I
Transmit Clock. Transmit demand clock. 0 to 52 MHz. Can be a gapped
clock. Fully independent of RCLK.
31
TDIS
I
Transmit Disable. Set high to hold the current bit being transmitted at
TDATA. Set low to allow the next bit to appear at TDATA. Should be
tied to VSS if not used. See Figure 7 for timing information. All transmit
side operations are disabled when TDIS is high.
32
TDATA
O
Transmit Data. Transmit NRZ serial data, updated on the rising edge of
TCLK.
DS2172 REGISTER MAP Table 2
ADDRESS
R/W
REGISTER NAME
ADDRESS
R/W
REGISTER NAME
00
R/W
Pattern Set Register 3.
0C
R
Bit Error Counter Register 3.
01
R/W
Pattern Set Register 2.
0D
R
Bit Error Counter Register 2.
02
R/W
Pattern Set Register 1.
0E
R
Bit Error Counter Register 1.
03
R/W
Pattern Set Register 0.
0F
R
Bit Error Counter Register 0.
04
R/W
Pattern Length Register.
10
R
Pattern Receive Register 3.
05
R/W
Polynomial Tap Register.
11
R
Pattern Receive Register 2.
06
R/W
Pattern Control Register.
12
R
Pattern Receive Register 1.
07
R/W
Error Insert Register.
13
R
Pattern Receive Register 0.
08
R
Bit Counter Register 3.
14
R
Status Register.
09
R
Bit Counter Register 2.
15
R/W
Interrupt Mask Register.
0A
R
Bit Counter Register 1.
1C
R/W
Test Register (see note 1)
0B
R
Bit Counter Register 0.
NOTE:
1. The Test Register must be set to 00 hex to insure proper operation of the DS2172.
相關(guān)PDF資料
PDF描述
DS2172 SPECIALTY TELECOM CIRCUIT, PQFP32
DS2175S DATACOM, ELASTIC BUFFER, PDSO16
DS2175 DATACOM, ELASTIC BUFFER, PDIP16
DS2175N DATACOM, ELASTIC BUFFER, PDIP16
DS2175SN DATACOM, ELASTIC BUFFER, PDSO16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2172TN/T&R 功能描述:電信集成電路 RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray
DS2172TN+ 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray
DS2172TN+T&R 制造商:Maxim Integrated Products 功能描述:BERT 32P TQFP T&R IND LEAD FREE - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC BIT ERROR RATE TESTER 32TQFP 制造商:Maxim Integrated Products 功能描述:Telecom ICs Bit Error Rate Tester (BERT)
DS2172TN+T&R 功能描述:電信集成電路 Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray
DS2174 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:EBERT
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