參數(shù)資料
型號(hào): DS2180A
英文描述: T1 Transceiver
中文描述: T1收發(fā)器
文件頁數(shù): 21/35頁
文件大?。?/td> 481K
代理商: DS2180A
DS2180A
21 of 35
RYEL OUTPUT
The yellow alarm output transitions high when a yellow alarm is detected. A high-low transition indicates
the alarm condition has been cleared. The RYEL bit (RSR.5) is a “l(fā)atched” version of the RYEL output.
In 193E framing, the yellow alarm pattern detected is 16 pattern sets of 00 (Hex) and FF (Hex) received
at RLINK. In 193S, framing the yellow alarm format is de-pendent on CCR.3; if CCR.3=0, the RYEL
output transitions high if bit 2 of 256 or more consecutive channels is 0; if CCR.3=1, yellow alarm is
declared when the S-bit received in frame 12 is 1.
RBV OUTPUT
The bipolar violation output transitions high when an accused bit emerges at RSER. RBV will go low at
the next bit time if no additional violations are detected.
RFER OUTPUT
The receive frame error output transitions high at the F-bit time and is held high for two bit periods when
a frame bit error occurs. In 193S framing, F
T
and F
S
patterns are tested. The FPS pattern is tested in 193E
framing. Additionally, in 193E framing, RFER reports a CRC error by a low-high-low transition (one bit
period wide) one half RCLK period before a low-high transition on RMSYNC.
RESET
A high-low transition on
RST
clears all registers and forces immediate receive resync when
RST
returns
high. This reset has no effect on transmit frame multiframe or channel counters.
RST
must be held low on
system power-up to insure proper initialization of transceiver counters and registers. Following reset, the
host processor should restore all control modes by writing appropriate registers with control data.
ALARM OUTPUT TIMING
Figure 21
NOTES:
1.
RFER transitions high during F-bit time if received framing pattern bit is in error. (Frame 12 F-bits in
193S are ignored if CCR.3=1). Also, in 193E, RFER transitions 1/2 bit time before the rising edge of
RMSYNC to indicate a CRC error for the previous multiframe.
2.
RBV indicates received bipolar violation and transitions high when an accused bit emerges from
RSER. If B8ZS is enabled, RBV will not report the zero replacement code.
3.
RCL transitions high (during 32nd bit time) when 32 consecutive bits received are 0; RCL transitions
low when the next 1 is received.
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