參數(shù)資料
型號(hào): DS21FF44
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, 1.27 MM PITCH, MCMBGA-300
文件頁(yè)數(shù): 46/110頁(yè)
文件大?。?/td> 526K
代理商: DS21FF44
DS21FT44/DS21FF44
40 of 110
SYMBOL
POSITION
NAME AND DESCRIPTION
Must be cleared and set again for a subsequent align. See
Section 17 for details.
TESALGN
CCR5.5
Transmit Elastic Store Align. Setting this bit from a zero to
a one may force the transmit elastic store’s write/read pointers
to a minimum separation of half a frame. No action will be
taken if the pointer separation is already greater or equal to
half a frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align. See
Section 17 for details.
RCM4
CCR5.4
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 13 for details.
RCM3
CCR5.3
Receive Channel Monitor Bit 3.
RCM2
CCR5.2
Receive Channel Monitor Bit 2.
RCM1
CCR5.1
Receive Channel Monitor Bit 1.
RCM0
CCR5.0
Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR6: COMMON CONTROL REGISTER 6 (Address=1D Hex)
(MSB)
(LSB)
TCLKSRC
RESR
TESR
SYMBOL
POSITION
NAME AND DESCRIPTION
CCR6.7
Not Assigned. Should be set to zero when written
CCR6.6
Not Assigned. Should be set to zero when written
CCR6.5
Not Assigned. Should be set to zero when written
CCR6.4
Not Assigned. Should be set to zero when written
CCR6.3
Not Assigned. Should be set to zero when written
TCLKSRC
CCR6.2
Transmit Clock Source Select. This function allows the user
to internally select RCLK as the clock source for the transmit
side formatter.
0 = Transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
RESR
CCR6.1
Receive Elastic Store Reset. Setting this bit from a zero to a
one will force the receive elastic store to a depth of one frame.
Receive data is lost during the reset. Should be toggled after
RSYSCLK has been applied and is stable. Do not leave this
bit set high.
TESR
CCR6.0
Transmit Elastic Store Reset. Setting this bit from a zero to
a one will force the transmit elastic store to a depth of one
frame. Transmit data is lost during the reset. Should be
toggled after TSYSCLK has been applied and is stable. Do
not leave this bit set high.
相關(guān)PDF資料
PDF描述
DS21FF44N DATACOM, FRAMER, PBGA300
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
DS21FT42N DATACOM, FRAMER, PBGA300
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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