參數(shù)資料
型號： DS21Q354DK
廠商： Maxim Integrated Products
文件頁數(shù)： 13/13頁
文件大小： 0K
描述： KIT DESIGN FOR DS21Q354
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，調(diào)幀器和線路接口裝置（LIU）
已用 IC / 零件： DS21Q354
DALLAS SEMICONDUCTOR
DS21Q352/DS21Q552/DS21Q354/DS21Q554 Preliminary Data Sheet
December 29, 1998
9
T2
RVSS1
–
Receive Analog Signal Ground
H19
RVSS2
–
Receive Analog Signal Ground
J18
RVSS2
–
Receive Analog Signal Ground
D4
RVSS3
–
Receive Analog Signal Ground
D5
RVSS3
–
Receive Analog Signal Ground
V20
RVSS4
–
Receive Analog Signal Ground
W19
RVSS4
–
Receive Analog Signal Ground
W1
TCHBLK1
O
Transmit Channel Block for SCT1.
F20
TCHBLK2
O
Transmit Channel Block for SCT2.
C11
TCHBLK3
O
Transmit Channel Block for SCT3.
U20
TCHBLK4
O
Transmit Channel Block for SCT4.
V10
TCHCLK1
O
Transmit Channel Clock for SCT1.
A18
TCHCLK2
O
Transmit Channel Clock for SCT2.
B8
TCHCLK3
O
Transmit Channel Clock for SCT3.
L18
TCHCLK4
O
Transmit Channel Clock for SCT4.
Y9
TCLK1
I
Transmit Clock for SCT1.
B19
TCLK2
I
Transmit Clock for SCT2.
B10
TCLK3
I
Transmit Clock for SCT3.
M19
TCLK4
I
Transmit Clock for SCT4.
V6
TCLKI1
I
Transmit Clock Input for the LIU on SCT1.
D19
TCLKI2
I
Transmit Clock Input for the LIU on SCT2.
C8
TCLKI3
I
Transmit Clock Input for the LIU on SCT3.
P20
TCLKI4
I
Transmit Clock Input for the LIU on SCT4.
W7
TCLKO1
O
Transmit Clock Output from the Framer on SCT1.
E18
TCLKO2
O
Transmit Clock Output from the Framer on SCT2.
A7
TCLKO3
O
Transmit Clock Output from the Framer on SCT3.
P19
TCLKO4
O
Transmit Clock Output from the Framer on SCT4.
U16
TEST
I
Test (0 = normal operation / 1 = tri-state all outputs).
V3
TLCLK1
O
Transmit Link Clock for SCT1.
E20
TLCLK2
O
Transmit Link Clock for SCT2.
D6
TLCLK3
O
Transmit Link Clock for SCT3.
T18
TLCLK4
O
Transmit Link Clock for SCT4.
W5
TLINK1
I
Transmit Link Data for SCT1.
E19
TLINK2
I
Transmit Link Data for SCT2.
C6
TLINK3
I
Transmit Link Data for SCT3.
T19
TLINK4
I
Transmit Link Data for SCT4.
R1
TNEGI1
I
Transmit Negative Data Input for the LIU on SCT1.
F19
TNEGI2
I
Transmit Negative Data Input for the LIU on SCT2.
D8
TNEGI3
I
Transmit Negative Data Input for the LIU on SCT3.
R20
TNEGI4
I
Transmit Negative Data Input for the LIU on SCT4.
T3
TNEGO1
O
Transmit Negative Data Output from Framer on SCT1.
B20
TNEGO2
O
Transmit Negative Data Output from Framer on SCT2.
D9
TNEGO3
O
Transmit Negative Data Output from Framer on SCT3.
N20
TNEGO4
O
Transmit Negative Data Output from Framer on SCT4.
W3
TPOSI1
I
Transmit Positive Data Input for the LIU on SCT1.
C20
TPOSI2
I
Transmit Positive Data Input for the LIU on SCT2.
A8
TPOSI3
I
Transmit Positive Data Input for the LIU on SCT3.
R19
TPOSI4
I
Transmit Positive Data Input for the LIU on SCT4.
V7
TPOSO1
O
Transmit Positive Data Output from Framer on SCT1.
C19
TPOSO2
O
Transmit Positive Data Output from Framer on SCT2.
C9
TPOSO3
O
Transmit Positive Data Output from Framer on SCT3.
N19
TPOSO4
O
Transmit Positive Data Output from Framer on SCT4.
Y2
TRING1
O
Transmit Analog Ring Output for SCT1.
Y4
TRING2
O
Transmit Analog Ring Output for SCT2.
Y6
TRING3
O
Transmit Analog Ring Output for SCT3.
Y8
TRING4
O
Transmit Analog Ring Output for SCT4.
W9
TSER1
I
Transmit Serial Data for SCT1.
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