參數(shù)資料
型號(hào): DS21Q43-ATN
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 22/60頁(yè)
文件大?。?/td> 0K
描述: IC FRAMER E1 QUAD 5V 128-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 72
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 32mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21Q43A
29 of 60
5.1 BPV or Code Violation Counter
Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16-bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6=0,
then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same
polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 code words
are not counted as BPVs. If CCR2.6=1, then the VCR counts code violations as defined in ITU O.161.
Code violations are defined as consecutive bipolar violations of the same polarity. In most applications,
the DS21Q43A should be programmed to count BPVs when receiving AMI code and to count CVs when
receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions.
The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be
greater than 10**-2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB)
(LSB)
V15
V14
V13
V12
V11
V10
V9
V8
VCR1
V7
V6
V5
V4
V3
V2
V1
V0
VCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
V15
VCR1.7
MSB of the 16-bit bipolar or code violation count.
V0
VCR2.0
LSB of the 16-bit bipolar or code violation count.
5.2 CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync
occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB)
(LSB)
(note 1)
CRC9
CRC8
CRCCR1
CRC7
CRC6
CRC5
CRC4
CRC3
CRC2
CRC1
CRC0
CRCCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
CRC9
CRCCR1.1
MSB of the 10-bit CRC4 error count.
CRC0
CRCCR2.0
LSB of the 10-bit CRC4 error count.
NOTE:
1. The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error
counter.
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