參數(shù)資料
型號(hào): DS21Q43-ATN
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 9/60頁(yè)
文件大?。?/td> 0K
描述: IC FRAMER E1 QUAD 5V 128-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 72
控制器類(lèi)型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 4.5 V ~ 5.5 V
電流 - 電源: 32mA
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21Q43A
17 of 60
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB)
(LSB)
ODF
TFPT
T16S
TUA1
TSiS
TSA1
TSM
TSIO
SYMBOL
POSITION
NAME AND DESCRIPTION
ODF
TCR1.7
Output Data Format.
0=bipolar data at TPOS and TNEG
1=NRZ data at TPOS; TNEG=0
TFPT
TCR1.6
Transmit Timeslot 0 Pass Through.
0=FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers
1=FAS bits/Sa bits/Remote Alarm sourced from TSER
T16S
TCR1.5
Transmit Timeslot 16 Data Select.
0=sample timeslot 16 at TSER pin
1=source timeslot 16 from TS0 to TS15 registers
TUA1
TCR1.4
Transmit Unframed All 1s.
0=transmit data normally
1=transmit an unframed all 1s code at TPOS and TNEG
TSiS
TCR1.3
Transmit International Bit Select.
0=sample Si bits at TSER pin
1=source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0)
TSA1
TCR1.2
Transmit Signaling All 1s.
0=normal operation
1=force timeslot 16 in every frame to all 1s
TSM
TCR1.1
TSYNC Mode Select.
0=frame mode (see the timing in Section 11)
1=CAS and CRC4 multiframe mode (see the timing in Section
11)
TSIO
TCR1.0
TSYNC I/O Select.
0=TSYNC is an input
1=TSYNC is an output
NOTE:
1. See Figure 11-9 for more details about how the Transmit Control Registers affect the operation of the
DS21Q43A.
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