參數(shù)資料
型號(hào)： DS2408S+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 39/39頁(yè)
文件大?。?/td> 0K
描述： IC SWITCH 8-CHAN ADDRESS 16SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 50
接口： 1 線
輸入/輸出數(shù)： 8
中斷輸出： 無(wú)
電源電壓： 2.8 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 管件
DS2408
9 of 39
PIO Logic-State Register
The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers
command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as
STRB
. See the Channel-Access commands description for details on STRB.
PIO Logic State Register Bitmap
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0088h
P7
P6
P5
P4
P3
P2
P1
P0
This register is read-only. Each bit is associated with the pin of the respective PIO channel as shown in
Figure 6. The data in this register is sampled at the last (most significant) bit of the byte that proceeds
reading the first (least significant) bit of this register. See the Read PIO Registers command description
for details.
PIO Output Latch State Register
The data in this register represents the latest data written to the PIO through the Channel-access Write
command. This register is read using the Read PIO Registers command. Reading this register does not
generate a signal at the RSTZ pin, even if it is configured as STRB. See the Channel-access commands
description for details on STRB. This register is not affected if the device reinitializes itself after an ESD
hit.
PIO Output Latch State Register Bitmap
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
0089h
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
This register is read-only. Each bit is associated with the output latch of the respective PIO channel as
shown in Figure 6.
The flip-flops of this register will power up in a random state. If the chip has to power up with all PIO
channels off, a LOW pulse must be generated on the RSTZ pin, e.g., by means of an open-drain CPU
supervisor chip (see Figure 20). When using an RC circuit to generate the power-on reset, make sure that
RSTZ is NOT configured as strobe output (ROS bit in control/status register 008Dh needs to be 0).
PIO Activity Latch State Register
The data in this register represents the current state of the PIO activity latches. This register is read using
the Read PIO Registers command. Reading this register does not generate a signal at the RSTZ pin, even
if it is configured as STRB. See the Channel-access commands description for details on STRB.
PIO Activity Latch State Register Bitmap
ADDR
b7
b6
b5
b4
b3
b2
b1
b0
008Ah
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
This register is read-only. Each bit is associated with the activity latch of the respective PIO channel as
shown in Figure 6. This register is cleared to 00h by a power-on reset, by a low pulse on the RSTZ pin
(only if RSTZ is configured as RST input), or by successful execution of the Reset Activity Latches
command.
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